UPD17708 datasheet(236/358 Pages) RENESAS

236 / 358 page

234

µPD17704, 17705, 17707, 17708, 17709

Figure 16-12. Shift Clock Generation Timing in I2C Bus Mode (4/5)

When the slave operation is specified the first time after application of supply voltage VDD, the SCK pin

waits for input of an external clock and the output pin goes into a high-impedance state.

If the SCL pin is externally made low at this time, it continues outputting a low level until the wait status

is released next time.

Figure 16-12. Shift Clock Generation Timing in I2C Bus Mode (5/5)

1/fSC

Wait request by slave

Wait released status

Shift clock

Wait request by slave cleared

0-3.3 s

Wait request by slave

Shift clock

Wait request by slave cleared

0-3.3 s

Wait period (originally, Hi-Z)

I/O port

Wait released period

Shift clock

Slave is set

Wait released

(8) Start and stop conditions, and operations of SBSTT and SBBSY flags

The start/stop condition recognition timing is shown in Figure 16-13.

The SBSTT and SBBSY flags operate only in the I2C bus mode.

By detecting these flags, communication status of the other stations can be detected.

These flags operate regardless of whether the device operates as the master or slave, whether it performs

reception or transmission, and whether communication is in the wait status or released from the wait status.

These flags are “0” in the serial I/O mode.

For the operations of the SBSTT and SBBSY flags, refer to Figure 16-10 Timing Chart in I2C Bus Mode.

UPD17708 Datasheet(PDF) 236 Page - Renesas Technology Corp