UPD17708 datasheet(234/358 Pages) RENESAS

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UPD17708 Datasheet(PDF) 234 Page - Renesas Technology Corp

Part #	UPD17708

Description	MOS INTEGRATED CIRCUIT

PDF	358 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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234 / 358 page

232

µPD17704, 17705, 17707, 17708, 17709

(7) Shift clock generation timing in I2C bus mode

(a) On releasing wait status from initial status

The initial status is the point where the master operation in the I2C bus mode is selected.

In the wait status, a low level is output to the shift clock pin.

Figure 16-12. Shift Clock Generation Timing in I2C Bus Mode (1/5)

Wait period

1/fSC

Shift clock

Wait released

Initialization

1 : 1

(b) During wait operation

<1> Wait status under condition of SIO0WRQ0 and SIO0WRQ1 flags (normal operation)

Figure 16-12. Shift Clock Generation Timing in I2C Bus Mode (2/5)

Wait period

Wait released status

1/fSC

Shift clock

Wait under condition of

SIO0WRQ1 and

SIO0WRQ0

Wait released

<2> If forced wait status is set in wait status

Nothing is affected.

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