UPD17708 datasheet(235/358 Pages) RENESAS

235 / 358 page

233

µPD17704, 17705, 17707, 17708, 17709

<3> If forced wait status is set after wait status has been released

In this case, the wait status is set at the next falling edge of the clock after the one at which the forced

wait status was set.

When the forced wait status was set, however, the clock counter and presettable shift register 0 stop

operating.

If the forced wait status is set while the clock pin is low, the clock counter and presettable shift register

0 operate by 1 pulse. Because the internal clock counter and shift register do not operate at this

time, communication may not be performed normally even if the wait status is released again.

Figure 16-12. Shift Clock Generation Timing in I2C Bus Mode (3/5)

1/fSC

Wait period

Wait pending

Wait released status

Shift clock

Wait period

1/fSC

Wait pending

Wait released

Forced wait set by

SIO0NWT

Forced wait set by

SIO0NWT

Wait released

<4> If wait status is released after wait status has been released

Nothing is affected.

<5> If wait request is made by slave after wait status has been released

At this time, the clock is output 0 to 3.3

µs after the wait request by the slave has been cleared.

The value of T in the figure below is as follows:

fSC

93.75 kHz

666 ns

375.00 kHz

222 ns

281.25 kHz

222 ns

46.875 kHz

666 ns

UPD17708 Datasheet(PDF) 235 Page - Renesas Technology Corp