UPD17708 datasheet(232/358 Pages) RENESAS

232 / 358 page

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µPD17704, 17705, 17707, 17708, 17709

(3) Operation of clock counter

The value of the clock counter is incremented from the initial value “0” each time the rising of the clock pin

has been detected.

In the I2C bus mode, the value of the clock counter returns to “0” after it has reached “9”, and the clock counter

continues counting.

In the serial I/O mode, the value of the clock counter returns to “0” after it has reached “8”, and the clock counter

continues counting.

The clock counter is also reset in the following cases.

•

At reset (power-ON reset, WDT&SP reset, CE reset)

•

On execution of clock stop instruction

•

On detection of start condition

•

If communication mode is changed from I2C bus mode to 2-wire or 3-wire serial I/O mode

(4) Wait operation and cautions

When the wait status is released, serial data is output (during transmission operation), and the wait status is

kept released until a condition (wait condition) set by the SIO0WRQ0 and 1 flags is satisfied.

When the wait condition is satisfied, the shift clock pin is made low, and the operations of the clock counter

and presettable shift register 0 are stopped.

If the forced wait status is specified while the wait status is released, the forced wait status is set at the falling

of the clock next to the one at which “0” has been written to the SIO0NWT flag.

Nothing is changed even if the wait status is released again after the wait status has been released once.

If the forced wait status is set in the wait status, one pulse of the shift clock is output.

In the I2C bus mode, do not set data wait conditions (SIOWRQ0 = 1, WIO0WRQ1 = 0) successively. This is

because, if the data wait condition is set two times in succession and the wait status is released, the wait status

is set as soon as the wait status has been released the second time.

While the device is operating as the master and if the level of the shift clock output pin is forcibly made low

externally while the pin outputs a high level (this is called a wait request by slave), the master is placed in the

wait status.

If this happens, the master resumes its operation when the wait request by the slave has been cleared.

(5) Interrupt request issuance timing

Interrupt request issuance timing can be selected by the SIO0IMD0 and 1 flags.

(6) Acknowledge block and its operation

The acknowledge block operates only in the I2C bus mode.

This block is used to output an acknowledge signal during a reception operation, or to detect an acknowledge

signal during a transmission operation.

During reception, the content of the SBACK flag is output to the serial data pin at the falling edge of the shift

clock when the value of the clock counter is “8”.

Once data has been set to the SBACK flag during reception, the value of the data is retained.

During transmission, the status of the serial data pin is read to the SBACK flag at the rising edge of the shift

clock when the value of the clock counter reaches “9”

Figure 16-11 shows the acknowledge signal output and input operations.

During reception, set the acknowledge signal (setting of the SBACK flag) as soon as the wait status has been

released (by setting the SIO0NWT flag).

UPD17708 Datasheet(PDF) 232 Page - Renesas Technology Corp

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