 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
UPD17708 Datasheet(PDF) 230 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
UPD17708 Datasheet(HTML) 230 Page - Renesas Technology Corp |
|
|
230 / 358 page  228 µPD17704, 17705, 17707, 17708, 17709 16.2.7 Interrupt control block The interrupt control block sets a condition under which an interrupt request is issued by the serial I/O0 interrupt mode selection register. When the interrupt request issuance condition is satisfied, the IRQSIO0 flag is set. Change the interrupt request issuance condition while communication is in the wait status. If it is changed after communication has been released from the wait status, an interrupt request may be issued as soon as the condition has been changed. Figure 16-9 shows the configuration of the serial I/O0 interrupt mode selection register. Figure 16-9. Configuration of Serial I/O0 Interrupt Mode Selection Register Notes 1. An interrupt request is issued if this mode is set when the value of the clock counter is “7”. 2. An interrupt request is issued if this mode is set when the value of the clock counter is “8”. 3. An interrupt request is issued if this mode is set when the SBSTT flag = 1 and the value of the clock counter is “7”. 4. An interrupt request is issued if this mode is set after the stop condition has been issued. Name Flag symbol b3 0 b2 0 b1 S I O 0 I M D 1 b0 S I O 0 I M D 0 Address 0CH Read/Write R/W Serial I/O0 interrupt mode selection Power-ON reset WDT & SP reset CE reset Clock stop 00 0 0 0 0 0 0 0 0 Rising edge of shift clock when value of clock counter reaches “7” Rising edge of shift clock when value of clock counter reaches “8” Rising edge of shift clock when value of clock counter reaches “7” after detection of start condition Note 3 When stop condition is detected Note 4 Rising edge of shift clock when value of clock counter reaches “7” Note 1 Rising edge of shift clock when value of clock counter reaches “8” Note 2 Interrupt request is not issued Sets interrupt request issuance condition Fixed to “0” 0 0 1 1 0 1 0 1 I2C bus mode Serial I/O mode |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
