UPD17708 datasheet(226/358 Pages) RENESAS

226 / 358 page

224

µPD17704, 17705, 17707, 17708, 17709

16.2.5 Presettable shift register 0

Presettable shift register 0 is an 8-bit shift register that writes serial out data and reads serial in data.

This register writes or reads data via data buffer.

It outputs the contents of the most significant bit (MSB) from the serial data I/O pin in synchronization with the falling

edge of the shift clock (during transmission operation), and reads data to the least significant bit (LSB) in synchronization

with the rising edge of the serial clock.

Figure 16-6 shows the configuration of the presettable shift register 0.

Figure 16-6. Configuration of Presettable Shift Register 0

Note

Data may be destroyed if the PUT or GET instruction is executed during serial communication. For details,

refer to 16.2.10 Causions on setting and reading data.

Name

Symbol Peripheral register

03H

Sets serial out data and reads serial in data

← D6 ← D5 ← D4 ← D3 ← D2 ← D1 ← D0

Serial out

Serial in

Peripheral register

SIO0SFR

Presettable shift

Valid data

D7 D6 D5 D4 D3 D2 D1 D0

DBF3

Data buffer

Don't care

Transfer data

DBF2

Don't care

DBF1

DBF0

GETNote

PUTNote

UPD17708 Datasheet(PDF) 226 Page - Renesas Technology Corp