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UPD17708 Datasheet(PDF) 224 Page - Renesas Technology Corp |
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UPD17708 Datasheet(HTML) 224 Page - Renesas Technology Corp |
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224 / 358 page  222 µPD17704, 17705, 17707, 17708, 17709 16.2.4 Clock counter and start/stop detection block The clock counter is a wrap-around counter that counts the rising edges of the clock. Because this counter directly reads the status of the clock pin, whether the clock is an internal clock or external clock cannot be identified. The contents of the clock counter can be detected via the SIO0SF8 and SIO0SF9 flags of the serial I/O0 status detection register, but cannot be directly read by program. The start/stop detection block detects the start and stop conditions when the I2C bus mode is used. The start and stop conditions are detected by the SBSTT and SBBSY flags of the serial I/O0 status detection register. Figure 18-5 shows the configuration of the serial I/O0 status detection register. For the operation and timing chart of the clock counter, refer to the description of each communication mode. |
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