Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

UPD17708 Datasheet(PDF) 223 Page - Renesas Technology Corp

Part # UPD17708
Description  MOS INTEGRATED CIRCUIT
PDF  358 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD17708 Datasheet(HTML) 223 Page - Renesas Technology Corp

Back Button UPD17708 Datasheet HTML 219Page - Renesas Technology Corp UPD17708 Datasheet HTML 220Page - Renesas Technology Corp UPD17708 Datasheet HTML 221Page - Renesas Technology Corp UPD17708 Datasheet HTML 222Page - Renesas Technology Corp UPD17708 Datasheet HTML 223Page - Renesas Technology Corp UPD17708 Datasheet HTML 224Page - Renesas Technology Corp UPD17708 Datasheet HTML 225Page - Renesas Technology Corp UPD17708 Datasheet HTML 226Page - Renesas Technology Corp UPD17708 Datasheet HTML 227Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 223 / 358 page
background image
221
µPD17704, 17705, 17707, 17708, 17709
16.2.3 Clock control block
The clock control block controls generation of a clock when the internal clock is used (master operation) and clock
output timing.
The frequency fSC of the internal clock is set by the SIO0CK1 and SIO0CK0 flags of the serial I/O0 clock selection
register.
Figure 16-4 shows the configuration of the serial I/O0 clock selection register.
The shift clock output from the clock control block is valid only for the master operation (SIO0MS flag = 1).
For the clock generation timing, refer to the description of each communication mode.
Figure 16-4. Configuration of Serial I/O0 Clock Selection Register
Name
Flag symbol
b3
0
b2
S
B
M
D
b1
S
I
O
0
C
K
1
b0
S
I
O
0
C
K
0
Address
0BH
Read/Write
R/W
Serial I/O0 clock selection
Power-ON reset
WDT&SP reset
CE reset
Clock stop
00
0
0
0
0
0
0
0
0
0
0
0
93.75 kHz
375.00 kHz
281.25 kHz
46.875 kHz
Selects internal shift clock frequency fSC of serial interface 0
Continues processing
Slave reception mode is set automatically if acknowledge signal is not
received (fixed to “1” when serial I/O is selected)
Selects operation mode during slave transmission of I2C bus
Fixed to “0”
0
1
0
0
1
1
0
1
0
1



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com