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UPD17708 Datasheet(PDF) 252 Page - Renesas Technology Corp |
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UPD17708 Datasheet(HTML) 252 Page - Renesas Technology Corp |
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252 / 358 page  250 µPD17704, 17705, 17707, 17708, 17709 (4) Interrupt request issuance timing An interrupt request is issued at the rising of the shift clock when the value of the clock counter is “8”. (5) Shift clock generation timing (a) On releasing wait status from initial status The initial status is the status when the P0B2/SCK1 pin is set in the output mode and the internal clock operation is selected. In the wait status, a high level is output to the shift clock pin. The wait status can be released and a clock can be selected at the same time. Figure 16-20. Shift Clock Generation Timing of Serial Interface 1 (1/4) 1/fSC Wait status Shift clock Wait released Initialization 1 : 1 (b) When wait operation is performed (normal operation) <1> If wait status is set at the 8th clock (normal operation) Figure 16-20. Shift Clock Generation Timing of Serial Interface 1 (2/4) Shift clock Wait Wait release period Wait period 1/fSC Wait released |
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