UPD17708 datasheet(269/358 Pages) RENESAS

269 / 358 page

267

µPD17704, 17705, 17707, 17708, 17709

17.6 Using PLL Frequency Synthesizer

To control the PLL frequency synthesizer, the following data is necessary.

(1) Division mode

: Direct division (MF), pulse swallow (HF, VHF)

(2) Pins used

: VCOL and VCOH pins

(3) Reference frequency : fr

(4) Division value

: N

17.6.1 through 17.6.3 below describe how to set PLL data in each division mode (MF, HF, and VHF).

17.6.1 Direct division mode (MF)

(1) Selecting division mode

Select the direct division mode by using the PLL mode selection register.

(2) Pins used

The VCOL pin is enabled to operate when the direct division mode is selected.

(3) Selecting reference frequency fr

Select the reference frequency by using the PLL reference frequency selection register.

(4) Calculation of division value N

Calculate N as follows:

N =

fVCOL

fVCOL : Input frequency of VCOL pin

: Reference frequency

(5) Example of setting PLL data

How to set data to receive broadcasting in the following MW band is described below.

Reception frequency

: 1422 kHz (MW band)

Reference frequency

: 9 kHz

Intermediate frequency : +450 kHz

Division value N is calculated as follows:

N =

fVCOL

1422 + 450

= 208 (decimal)

= 0D0H (hexadecimal)

Set data to the PLL data register, PLL mode selection register, and PLL reference frequency selection register

as follows:

UPD17708 Datasheet(PDF) 269 Page - Renesas Technology Corp