UPD17708 datasheet(271/358 Pages) RENESAS

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269

µPD17704, 17705, 17707, 17708, 17709

17.6.2 Pulse swallow mode (HF)

(1) Selecting division mode

Select the pulse swallow mode by using the PLL mode selection register.

(2) Pins used

The VCOL pin is enabled to operate when the pulse swallow mode is selected.

(3) Selecting reference frequency fr

Select the reference frequency by using the PLL reference frequency selection register.

(4) Calculation of division value N

Calculate N as follows:

N =

fVCOL

fVCOL : Input frequency of VCOL pin

: Reference frequency

(5) Example of setting PLL data

How to set data to receive broadcasting in the following SW band is described below.

Reception frequency

: 25.50 MHz (SW band)

Reference frequency

: 5 kHz

Intermediate frequency : +450 kHz

Division value N is calculated as follows:

N =

fVCOL

25500 + 450

= 5190 (decimal)

= 1446H (hexadecimal)

Set data to the PLL data register, PLL mode selection register, and PLL reference frequency selection register

as follows:

Caution The division value N is 17 bits long when the pulse swallow mode is selected, and the least

significant bit of the swallow counter is the bit 3 of the PLL mode selection register (PLLSCNF).

To set “1446H” as the division value N, the value to be actually set to the PLL data register

is “0A23H”.

Note

PLLSCNF flag

PLL data register (PLLR)

0 0

PLL mode

selection

PLL reference

frequency

selection register

Note

5 kHz

UPD17708 Datasheet(PDF) 271 Page - Renesas Technology Corp

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