EP1C3 datasheet(32/104 Pages) ALTERA

32 / 104 page

2–26

Altera Corporation

Preliminary

January 2007

Cyclone Device Handbook, Volume 1

Figure 2–18. Input/Output Clock Mode in True Dual-Port Mode

Note (1), (2)

Notes to Figure 2–18:

(1)

All registers shown have asynchronous clear ports.

(2)

Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both

read and write operations.

ENA

data

A[ ]

address

A[ ]

Memory Block

256

× 16 (2)

512

× 8

1,024

× 4

2,048

× 2

4,096

× 1

Data In

Address A

Write/Read

Enable

Data Out

Data In

Address B

Write/Read

Enable

Data Out

clken

clock

ENA

wren

6 LAB Row Clocks

A[ ]

data

B[ ]

address

B[ ]

clken

clock

wren

B[ ]

ENA

byteena

A[ ]

Byte Enable A

Byte Enable B

byteena

B[ ]

ENA

Write

Pulse

Generator

Write

Pulse

Generator

EP1C3 Datasheet(PDF) 32 Page - Altera Corporation

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