RT7207 datasheet(22/25 Pages) RICHTEK

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RT7207

DS7207-00 January 2017

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Internal Biases and Charge Pump

The RT7207 provides three regulated bias voltages, V5,

V2, and V9. The V5 bias voltage is the output of a linear

regulator powered by VDD, and supplies the internal analog

circuit and the charge pump driver. The V2 bias voltage is

the output of a linear regulator powered by V5, and supplies

the MCU. As shown in Figure 8, the RT7207 also

integrates a charge pump circuit to generate V9 to supply

for the SR driver when VDD is at lower levels, such as

3.3V to 5V. If the RT7207 enters power-saving mode, the

charge pump driver will be disabled.

The minimum source/sink capability of charge pump driver

is around 10mA at 170kHz of charge pump operating

frequency fCP. Bypass capacitor on the V5, V2 and V9

pins are required to minimize output ripples of the biases.

V9 = V5 x 2

− VF_DCP1 − VF_DCP2 − IV9 x ROUT_CP

When output voltage is set at lower levels (<5V), V5 will

be lower, following VDD by a voltage drop of a dropout

voltage of the LDO. For higher V9, a lower forward voltage

for the Schottky diodes, DCP1 and DCP2, is required.

The RT7207 provides V5 short-circuit protection against

the condition that the V5, V2, or VCP pin is shorted to

GND, and also provides under-voltage protection for V9. If

the V9 voltage is below VV9_SRON (typical 4.5V), the SR

driver will be turned off, that is, VG will be inactivated.

Output Voltage Rises and Falls

When the protocol is detected, the reference voltage

VREF_CV can be set by the request of the UFP. Both the

rise time and fall time of output voltages should be less

than 275ms in accordance with the USB PD Specification,

as shown in Figure 9.

During the time of VOUT falling, as shown in Figure 10, the

BLD driver will be turned on as a dummy load to provide

an extra discharging path for the output capacitor so that

VOUT can be settled in a shorter duration. The designed

RDUMMY is as :

COUT x (RDUMMY + RL_BLD) x 2 < 275ms

During the time of VOUT rising or falling, the SR driver will

be turned off. After a firmware programmable delay time

300ms, the RT7207 will sense the load condition and may

reactivate the SR driver.

(a)

Figure 7. The Waveforms of the Bias Voltages during

Start-Up

Figure 8. Charge Pump Circuit

VDD

IOUT

Power-saving mode

threshold

Power-Saving

Mode

VVDD_ON

Debounce time to enter power-saving mode

VCP

CV9

CV5

DCP1

CCP

IV9

DCP2

ROUT_CP

20V

0.625V

<275ms

VOUT

VREF_CV

2.5V

SR_EN

5ms

Slope 1.875V / 275ms

5mV/750µs



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RT7207 Datasheet(PDF) 22 Page - Richtek Technology Corporation

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