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RT7207 Datasheet(PDF) 24 Page - Richtek Technology Corporation |
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RT7207 Datasheet(HTML) 24 Page - Richtek Technology Corporation |
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24 / 25 page ![]() RT7207 24 DS7207-00 January 2017 www.richtek.com © Copyright 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Figure 12. OVP Pin Block Diagram Figure 13. Timing Sequence of the OVP Pin Function Thermal Considerations The junction temperature should never exceed the absolute maximum junction temperature TJ(MAX), listed under Absolute Maximum Ratings, to avoid permanent damage to the device. The maximum allowable power dissipation depends on the thermal resistance of the IC package, the PCB layout, the rate of surrounding airflow, and the difference between the junction and ambient temperatures. The maximum power dissipation can be calculated using the following formula : PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TAis the ambient temperature, and θJA is the junction-to-ambient thermal resistance. For continuous operation, the maximum operating junction temperature indicated under Recommended Operating Conditions is 125 °C. The junction-to-ambient thermal resistance, θJA, is highly package dependent. For a WQFN-24L 4x4 package, the thermal resistance, θJA, is 28 °C/W on a standard JEDEC 51-7 high effective-thermal- conductivity four-layer test board. The maximum power dissipation at TA = 25 °C can be calculated as below : PD(MAX) = (125 °C − 25°C) / (28°C/W) = 3.57W for a WQFN-24L 4x4 package. The maximum power dissipation depends on the operating ambient temperature for the fixed TJ(MAX) and the thermal resistance, θJA. The derating curves in Figure 14 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. Figure 14. Derating Curve of Maximum Power Dissipation 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 25 50 75 100 125 Ambient Temperature (°C) Four-Layer PCB VREF_CV OPTO R1 BLD_EN RD + - x1.2/x1.25/x1.3 + - VFB RFB1 RFB2 RV CV VDD RD2 R S Q VVDD_OFF ADC MCU INT_ “VDDOV” VOUT A OVP VOUT INT_VDDOV VOVP OV hys tD_VOUTOVP VDD = VVDD_OFF Debounce time of latched OPTO by MCU is around 10µs |
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