Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

SST55LD019C Datasheet(PDF) 71 Page - Silicon Storage Technology, Inc

Part # SST55LD019C
Description  ATA Flash Disk Controller
PDF  79 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  SST [Silicon Storage Technology, Inc]
Direct Link  http://www.sst.com/
Logo SST - Silicon Storage Technology, Inc

SST55LD019C Datasheet(HTML) 71 Page - Silicon Storage Technology, Inc

Back Button SST55LD019C Datasheet HTML 67Page - Silicon Storage Technology, Inc SST55LD019C Datasheet HTML 68Page - Silicon Storage Technology, Inc SST55LD019C Datasheet HTML 69Page - Silicon Storage Technology, Inc SST55LD019C Datasheet HTML 70Page - Silicon Storage Technology, Inc SST55LD019C Datasheet HTML 71Page - Silicon Storage Technology, Inc SST55LD019C Datasheet HTML 72Page - Silicon Storage Technology, Inc SST55LD019C Datasheet HTML 73Page - Silicon Storage Technology, Inc SST55LD019C Datasheet HTML 74Page - Silicon Storage Technology, Inc SST55LD019C Datasheet HTML 75Page - Silicon Storage Technology, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 71 / 79 page
background image
Data Sheet
ATA Flash Disk Controller
SST55LD019A / SST55LD019B / SST55LD019C
©2006 Silicon Storage Technology, Inc.
S71241-04-000
12/06
71
FIGURE
12-7: Host Terminates a Multi-word DMA Data Transfer
12.2.4 Media Side Interface I/O Timing Specifications
Note: All AC specifications are guaranteed by design.
TABLE 12-12: SST55LD019A/B/C Timing Parameters
Symbol
Parameter
Min
Max
Units
TCLS
FCLE Setup Time
20
-
ns
TCLH
FCLE Hold Time
40
-
ns
TCS
FCE# Setup Time
40
-
ns
TCH
FCE# Hold Time for Command/Data Write Cycle
40
-
ns
TCHR
FCE# Hold Time for Sequential Read Last Cycle
-
40
ns
TWP
FWE# Pulse Width
20
-
ns
TWH
FWE# High Hold Time
20
-
ns
TWC
Write Cycle Time
40
-
ns
TALS
FALE Setup Time
20
-
ns
TALH
FALE Hold Time
40
-
ns
TDS
FAD[15:0] Setup Time
20
-
ns
TDH
FAD[15:0] Hold Time
20
-
ns
TRP
FRE# Pulse Width
20
-
ns
TRR
Ready to FRE# Low
40
-
ns
TREA
FRE# Data Setup Access Time
20
-
ns
TRC
Read Cycle Time
40
-
ns
TREH
FRE# High Hold Time
30
-
ns
TRHZ
FRE# High to Data Hi-Z
5
-
ns
T12-12.0 1241
Write DQ15-0
Read DQ15-0
IORD#/IOWR
DMACK#
DMARQ
CS1FX#/CS3FX#
1241 F08.0
T0
TD
TK
TE
TN
TZ
TJ
TF
TH
TG
Note: 1. To terminate the transmission of a data burst, the host should negate DMACK# within the
specified time after a IORD# or IOWR# pulse. No further IORD# or IOWR# pulses shall be
asserted for this burst.
2. If the device is able to continue the transfer of data, the device may leave DMARQ asserted
and wait for the host to reassert DMACK# or may negate DMARQ at any time after detecting
that DMACK# has been negated.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com