MP2696B datasheet(18/34 Pages) MPSIND

18 / 34 page

MP2696B

– SW CHARGER WITH I2C CONTROL, BOOST OUTPUT

MP2696B Rev. 1.0

MonolithicPower.com

4/16/2021

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

USB2 Plug-In Detection

If the USB2_EN_PLUG bit is enabled in

standby mode, the SYS voltage (VSYS) is pulled

up to the BATT voltage (VBATT). After VSYS

reaches 90% of VBATT, detection starts. Once

VSYS drops to 75% of VBATT, the USB2 plug-in is

detected, the USB2_PLUG_IN bit is set to 1,

and an INT pulse is generated.

The host can respond to the interrupt signal and

enable boost mode Q2.

The host must clear the USB2_PLUG_IN bit,

and toggle the USB2_EN_PLUG bit for the next

detection.

Note

that

writing

the

USB2_PLUG_IN bit clears it to 0.

No-Load Detection

During boost or pass-through operation, the Q2

current is monitored. If the Q2 current is below

the value set by NOLOAD_THR, bits[1:0], the

NO_LOAD bit is set to 1, and an INT pulse is

generated. The host can monitor the NO_LOAD

bit to decide whether boost mode or Q2 must

be turned off.

Thermal Shutdown

The IC continuously monitors the internal

junction

temperature

maximize

power

delivery and avoid overheating the chip. If the

junction

temperature

reaches

150°C,

the

converter

shuts

down.

the

junction

temperature drops to 120°C, normal operation

resumes.

Battery Current Analog Output

The device has an IB pin to obtain the real-time

battery current value in both charge and boost

mode. The voltage at IB is a fraction of the

battery current. The IB pin indicates the current

flowing in and out of the battery during charge

and boost mode.

With a 10m

Ω current-sense resistor. calculate

the voltage at IB for charge mode and boost

mode with Equation (4) and Equation (5),

respectively:

VIB = ICHG x 0.35(V)

(4)

VIB = IDSCHG x 0.16(V)

(5)

Note that scaling the current-sense resistor also

scales the gain of IB.

Idle Mode

When the input power source is not present and

boost mode is disabled, the IC goes into idle

mode. In idle mode, all the MOSFETs and most

of the internal circuits are turned off to minimize

leakage and extend the battery run time.

SYS DP/DM Signaling

Initially, the DP and DM pins are biased at 2.7V

with an internal resistance of 30k

Ω for non-

standard adapter imitation.

If the DP or DM pin is out of the 2.1V to 2.9V

range for 10ms in DCP mode, the 2.7V

reference is disconnected, and DP and DM are

tied together with a 100

Ω resistor.

If DP stays below 0.35V for 2 seconds in DCP

mode, the IC returns to non-standard adapter

mode with DP/DM biased at 2.7V.

Series Interface

The IC uses an I2C-compatible interface for

flexible

charging

parameter

setting

and

instantaneous device status reporting. I2C is a

2-wire serial interface with two bus lines

required: a serial data line (SDA) and a serial

clock line (SCL). Both SDA and SCL lines are

open drain and must be connected to the

positive supply voltage via a pull-up resistor.

The IC operates as a slave device, receiving

control inputs from the master device such as a

microcontroller. The SCL line is always driven

the

master

device.

The

I2C

interface

supports both standard mode (up to 100kb/s),

and fast mode (up to 400kb/s).

All transactions begin with a start (S) condition

and are terminated by a stop (P) condition. The

start and stop conditions are always generated

by the master. A high to low transition on the

SDA line while SCL is high defines a start

condition. A low to high transition on the SDA

line when the SCL is high defines a stop

condition (see Figure 6).

SDA

SCL

Start (S)

Stop (P)

Figure 6: Start and Stop Conditions

MP2696B Datasheet(PDF) 18 Page - MPS Industries, Inc.

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