MP2696B datasheet(19/34 Pages) MPSIND

19 / 34 page

MP2696B

– SW CHARGER WITH I2C CONTROL, BOOST OUTPUT

MP2696B Rev. 1.0

MonolithicPower.com

4/16/2021

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

For data validity, the data on the SDA line must

be stable during the high period of the clock.

The high or low state of the SDA line can only

change when the clock signal on the SCL line is

low. Every byte on the SDA line must be 8 bits

long. The number of bytes to be transmitted per

transfer is unrestricted. Data is first transferred

with the most significant bit (MSB) (see Figure

7).

Data line

stable

Data valid

Change

of data

allowed

SDA

SCL

Figure 7: Bit Transfer on the I2C Bus

Each

byte

has

followed

acknowledge (ACK) bit, which is generated by

the receiver, to signal to the transmitter that the

byte was successfully received.

The ACK signal is defined as follows: the

transmitter releases the SDA line during the

acknowledge clock pulse so the receiver can

pull the SDA line low. The SDA line remains low

during the high period of the ninth clock.

If SDA line is high during the ninth clock, this is

defined as the not acknowledge (NACK) signal.

The master can then generate either a stop

condition to abort the transfer or a repeated

start (Sr) condition to start a new transfer.

After the start signal is received, a slave

address is sent. This address is 7 bits long,

followed by the eighth bit as a data direction bit

(bit R/W). A zero indicates a transmission

(write), and a one indicates a request for data

(read).

Figure

shows

the

address

bit

arrangement.

MSB

LSB

R/W

Slave Address

Figure 8: 7-Bit Address

See Figure 9 through Figure 13 for detailed

signal sequences.

SDA

SCL

Start or

Repeated

Start

MSB

Acknowledgement

signal from slave

ACK

Acknowledgement

signal from receiver

Stop or

Repeated

Start

Figure 9: Data Transfer on the I2C Bus

Slave Address

ACK

Reg Address

ACK

Data Address

ACK

Figure 10: Single Write

Slave Address

ACK

Reg Address

ACK

Data

NACK

Slave Address

ACK

Figure 11: Single Read

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