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MP2696B Datasheet(PDF) 26 Page - MPS Industries, Inc.

Part # MP2696B
Description  I2C-Controlled, Single-Cell Switching Charger with Power-Path Management,Boost Output, and 3.5A Input Current Limit
PDF  34 Pages
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Manufacturer  MPSIND [MPS Industries, Inc.]
Direct Link  http://www.mpsind.com/index.html
Logo MPSIND - MPS Industries, Inc.

MP2696B Datasheet(HTML) 26 Page - MPS Industries, Inc.

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MP2696B
– SW CHARGER WITH I2C CONTROL, BOOST OUTPUT
MP2696B Rev. 1.0
MonolithicPower.com
26
4/16/2021
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2021 MPS. All Rights Reserved.
REG07h
Bit
Name
POR
Reset by
REG_RST
R/W
Description
Comment
7
NOLOAD_
THR[1]
0
Y
R/W
00: 30mA
01: 50mA
10: 75mA
11: 100mA
These bits set the SYS no
load current threshold. This bit
is set to 00 by default.
6
NOLOAD_
THR[0]
0
Y
R/W
5
BATT_OVP
0
Y
R
0: The battery is operating
normally
1: Battery over-voltage
protection (OVP) has occurred
4
NTC_STOP
1
Y
R/W
0: Only report in the register if
NTC is outside its threshold
1: Suspend the charge and
boost operation if NTC is
outside its threshold
3
VIN_OVP
0
Y
R/W
0: 6V
1: 11V
This bit sets the VIN over-
voltage
protection
(OVP)
threshold.
2
SW_FREQ
0
Y
R/W
0: 700kHz
1: 1200kHz
This bit is set to 0 by default.
1
BST_IPK[1]
1
Y
R/W
00: 5A
01: 5.5A
10: 6A
11: 6.5A
These bits set the low-side
switch peak current limit in
boost mode. These bits are
set to 11 by default.
0
BST_IPK[0]
1
Y
R/W
REG08h
Bit
Name
POR
Reset by
REG_RST
R/W
Description
Comment
7
JEITA_VSET
1
Y
R/W
0: VBATT_REG - 100mV
1: VBATT_REG - 200mV
This bit is set to 1 by default.
6
JEITA_ISET
1
Y
R/W
0: 14.3% of ICC
1: 50% of ICC
This bit is set to 1 by default.
5
VHOT
1
Y
R/W
0: 34%
1: 36%
This bit sets the hot threshold.
This bit is set to 1 by default.
4
VWARM[1]
0
Y
R/W
00: 44%
01: 40%
10: 38%
11: 36%
These bits sets the warm
threshold. These bits are set
to 01 by default.
3
VWARM[0]
1
Y
R/W
2
VCOOL[1]
1
Y
R/W
00: 72%
01: 68%
10: 64%
11: 60%
These
bit
sets
the
cool
threshold. These bit are set to
11 by default.
1
VCOOL[0]
1
Y
R/W
0
VCOLD
0
Y
R/W
0: 72%
1: 68%
This
bit
sets
the
cold
threshold. This bit is set to 0
by default.



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