MPM3650

– 6A, 17V, 6A, 1.2MHz, STEP-DOWN POWER MODULE WITH DCM

MPM3650 Rev. 1.1

MonolithicPower.com

14

9/17/2021

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2021 MPS. All Rights Reserved.

Once VIN exceeds the UVLO rising threshold, the

MPM3650 starts up. If VIN drops below the UVLO

falling threshold, the device shuts. UVLO is a

non-latch protection.

Soft Start (SS)

The MPM3650 employs soft start (SS) to ensure

that the output ramps up smoothly during start-

up. If the EN pin goes high, an internal current

source (6

μA) charges the SS capacitor (CSS). As

the device starts up, the SS voltage (VSS) takes

over VREF to the PWM comparator. VOUT ramps

up smoothly with VSS. Once VSS exceeds VREF,

VSS continues to ramp up until VREF takes over.

Then SS finishes, and the device enters steady

state operation. The SS capacitance (CSS) can

be calculated with Equation (1):



 SS

SS

SS

REF

t

(ms) I (

μA)

C (nF)

0.83

V

(V)

(1)

It is recommended that CSS be an internal 22nF

capacitor. If the output capacitor (COUT) has a

large capacitance, it is not recommended to set

the soft-start time (tSS) too short, or else the

device could too easily reach the current limit

during SS.

Power Good (PG) Indicator

The PG pin is the open drain of a MOSFET that

connects to VCC or a voltage source via a

resistor (e.g. 100k

Ω). If VIN is applied and the PG

pin is pulled to PGND before SS completes, then

the MOSFET turns on. Once VFB reaches 90% of

VREF, PG is pulled high after a 50μs delay. Once

VFB drops below 80% of VREF, PG is pulled low.

If UVLO or over-temperature protection (OTP)

occurs, PG is pulled low. If an over-current (OC)

condition occurs and VFB drops below 80% of

VREF, PG is pulled low after a 0.05ms delay. If an

over-voltage (OV) condition occurs and VFB

exceeds 120% of VREF, PG is pulled low after a

0.05ms delay. If VFB drops below 110% of VREF,

PG is pulled high after a 0.05ms delay.

If the input supply fails to power the MPM3650,

PG is clamped low, even if PG is tied to an

external DC source via a pull-up resistor. Figure

4 shows the relationship between the PG voltage

(VPG) and the pull-up current.

Figure 4: Clamped VPG vs. Pull-Up Current

Over-Current Protection (OCP) and Short-

Circuit Protection (SCP)

The MPM3650 offers valley limit control. The

LS-FET monitors the current flowing through

itself. The HS-FET waits until the valley current

limit is not triggered before turning on again. VOUT

decreases until VFB drops below the under-

voltage (UV) threshold (typically 50% below

VREF). Once a UV fault occurs, the MPM3650

enters hiccup mode to periodically restart the

part.

During over-current protection (OCP), the device

tries to recover from the OC fault using hiccup

mode. The MPM3650 disables the output power

stage, discharges CSS, and initiates a SS. If the

OC condition remains after SS is complete, the

device repeats this operation until the OC

condition disappears, and the output rises back

to its regulation level. OCP is a non-latch

protection.

Pre-Biased Start-Up

The MPM3650 is designed for monotonic start-

up into pre-biased loads. If the output is pre-

biased to a certain voltage during start-up, and

the bootstrap (BST) voltage (VBST) is refreshed

and charged, then the VSS is also charged. If VBST

exceeds its rising threshold and VSS exceeds the

sensed VOUT at the FB pin, the part resumes

normal operation.

0

0.2

0.4

0.6

0.8

1

1.2

0

1

2

3

4

5

PULL-UP CURRENT (mA)