ES9080 datasheet(114/146 Pages) ESS

114 / 146 page

CONFIDENTIAL ADVANCE INFORMATION 0.4.3

ES9080 Product Datasheet

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM

114

Bits

[23]

[22]

[21]

[20]

[19]

[18:10]

[9:1]

[0]

Default

1'b0 1'b0 1'b0 1'b0 1'b0 9'd0

9'd0

1'b0

Bits

Mnemonic

Description

[23]

PLL_REG_PDB_HV

Power Down the HV regulator.

•

1'd0: Disable the PLL HV-regulator

•

1'd1: Enable the PLL HV-regulator

[22]

PLL_REG_PDB_1V2

Power Down the 1V2 regulator.

•

1'd0: Disable the PLL 1V2-regulator

•

1'd1: Enable the PLL 1V2-regulator

[21:20]

RESERVED

[19]

PLL_LOW_BW

Adjust the PLL Bandwidth

•

1’b0: Default

•

1’b1: Normal operation, optimum setting

[18:10]

PLL_CLK_OUT_DIV

Sets the Output Division (No) of the PLL.

•

9’d0: Reserved

•

9’d1: Divide by 1 (Normal Starting value)

•

9’d2: Divide by 2

•

9’dn: Divide by n

[9:1]

PLL_CLK_IN_DIV

Sets the PLL clock input divider.

•

9'd0: Reserved

•

9'd1: Divide by 1 (Normal Starting value)

•

9'd2: Divide by 2

•

9'dn: Divide by n

[0]

PLL_FB_DIV_LOAD

Load PLL_CLK_FB_DIV

Write 1 then write 0 to load CLK_FB_DIV.

ES9080 Datasheet(PDF) 114 Page - ESS Technology,Inc

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