TLK1221 datasheet(10/23 Pages) TI

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5pF

50 W

CLOCK

80%

50%

20%

0.8V

DATA

1.4V

LVTTL OUTPUT SWITCHING CHARACTERISTICS

TRANSMITTER TIMING REQUIREMENTS

TLK1221

SLLS713 – FEBRUARY 2007

Figure 8. Transmitter Test Setup

Figure 9. TTL Data I/O Valid Levels for AC Measurement

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tr(RBC)

Clock rise time

0.3

1.5

tf(RBC)

Clock fall time

0.3

1.5

80% to 20% output voltage, C = 5 pF (see

Figure 9)

Data rise time

0.3

1.5

Data fall time

0.3

1.5

TBI normal mode (see Figure 3), Rω = 125 MHz,

2.5

data valid prior to RBC0 rising

Data setup time

tsu(d1)

(RD0–RD9)

TBI normal mode (see Figure 3), Rω= 61.44

MHz, data valid prior to RBC0 rising

TBI normal mode (see Figure 3), Rω = 125 MHz,

data valid after RBC0 rising

th(d1)

Data hold time (RD0–RD9)

TBI normal mode (see Figure 3), Rω = 61.44

MHz, data valid after RBC0 rising

Data setup time

TBI half-rate mode, Rω = 125 MHz (see

tsu(d3)

2.5

(RD0–RD9)

Figure 2)

TBI half-rate mode, Rω = 125 MHz (see

th(d3)

Data hold time (RD0–RD9)

1.5

Figure 2)

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tsu(d4)

Data setup time (TD0–TD9)

1.6

th(d4)

Data hold time (TD0–TD9)

0.8

tr, tf

TD[0,9] data rise and fall time

See Figure 9

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