ADC32RF52 datasheet(70/108 Pages) TI

70 / 108 page

Figure 7-62. Register 0x22 (JESD page)

JESD MODE

R/W-0

Table 7-67. Register 0x22 Field Descriptions

Bit

Field

Type

Reset

Description

7:0

JESD MODE

R/W

00000000

This register sets the LMFS configuration

0: LMFS = 8-2-8-20 (also bit DROP LSB in 0x27 needs to be

set)

1: LMFS = 8-2-2-4

3: LMFS = 8-4-2-2

4: LMFS = 8-16-4-1

5: LMFS = 4-16-8-1

6: LMFS = 2-16-16-1

7: LMFS = 1-16-32-1

8: LMFS = 8-8-2-1

9: LMFS = 4-8-4-1

10: LMFS = 2-8-8-1

11: LMFS = 1-8-16-1

12: LMFS = 4-4-2-1

13: LMFS = 2-4-4-1

14: LMFS = 1-4-8-1

15: LMFS = 2-2-2-1

16: LMFS = 1-2-4-1

others: not used

Figure 7-63. Register 0x24 (JESD page)

DDC CLK DIV

R/W-0

Table 7-68. Register 0x24 Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DDC CLK DIV

R/W

00000000

This register sets the internal clock divider when using the

decimation filter. SeeTable 7-70 .

Figure 7-64. Register 0x25 (JESD page)

JESD TX CLK DIV

R/W-0

Table 7-69. Register 0x25 Field Descriptions

Bit

Field

Type

Reset

Description

7-0

JESD TX CLK DIV

R/W

0000000

This register sets the internal clock divider for the selected

LMFS output mode. See Table 7-70 for 16-bit and Table 7-71

for 20-bit output.

ADC32RF52

SBASAI6 – SEPTEMBER 2023

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