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ADC32RF52 Datasheet(PDF) 71 Page - Texas Instruments |
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ADC32RF52 Datasheet(HTML) 71 Page - Texas Instruments |
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71 / 108 page ![]() Table 7-70. Register Settings for 0x24/0x25 Based on Bypass/Decimation and LMFS Mode (16-bit Output) 0x24 (DDC CLK DIV) 0x25 (JESD TX CLK DIV) LMFS BYP /4 /8 /16 /32 /64 /128 BYP /4 /8 /16 /32 /64 /128 8-2-2-4 0 0 8-2-8-20 0 4 8-4-8-10 1 4 8-4-2-2 1 0 0 0 0 0 1 1 1 1 8-8-2-1 0 0 0 0 0 0 0 0 0 0 8-16-4-1 1 1 1 1 1 1 0 0 0 0 0 0 4-2-2-2 0 0 0 0 0 0 1 1 1 1 1 1 4-4-2-1 0 0 0 0 0 0 0 0 0 0 4-8-4-1 1 1 1 1 1 1 0 0 0 0 0 0 4-16-8-1 3 3 3 3 3 3 0 0 0 0 0 0 2-2-2-1 0 0 0 0 0 0 0 0 0 0 2-4-4-1 1 1 1 1 1 1 0 0 0 0 0 0 2-8-8-1 3 3 3 3 3 3 0 0 0 0 0 0 2-16-16-1 7 7 7 7 7 0 0 0 0 0 1-2-4-1 1 1 1 1 1 1 0 0 0 0 0 0 1-4-8-1 3 3 3 3 3 3 0 0 0 0 0 0 1-8-16-1 7 7 7 7 7 0 0 0 0 0 1-16-32-1 15 15 15 15 0 0 0 0 Table 7-71. Register Settings for 0x24/0x25 Based on Decimation and LMFS Mode (20-bit Output). 0x24 (DDC CLK DIV) 0x25 (JESD TX CLK DIV) LMFS BYP /4 /8 /16 /32 /64 /128 BYP /4 /8 /16 /32 /64 /128 8-8-4-1 1 1 1 1 1 1 0 0 0 0 0 0 8-16-8-1 3 3 3 3 3 3 0 0 0 0 0 0 4-4-4-1 1 1 1 1 1 1 0 0 0 0 0 0 4-8-8-1 3 3 3 3 3 3 0 0 0 0 0 0 4-16-16-1 7 7 7 7 7 0 0 0 0 0 2-2-4-1 1 1 1 1 1 1 0 0 0 0 0 0 2-4-8-1 3 3 3 3 3 3 0 0 0 0 0 0 2-8-16-1 7 7 7 7 7 0 0 0 0 0 2-16-32-1 15 15 15 15 0 0 0 0 1-2-8-1 3 3 3 3 3 3 0 0 0 0 0 0 1-4-16-1 7 7 7 7 7 0 0 0 0 0 1-8-32-1 15 15 15 15 0 0 0 0 1-16-64-1 31 31 31 0 0 0 www.ti.com ADC32RF52 SBASAI6 – SEPTEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 71 Product Folder Links: ADC32RF52 |
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