ADC32RF52 datasheet(98/108 Pages) TI

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8.5 Layout

8.5.1 Layout Guidelines

There are several critical signals which require specific care during board design:

1. Analog input and clock signals

• Traces should be as short as possible and vias should be avoided where possible to minimize impedance

discontinuities.

• Traces should be routed using loosely coupled 100-Ω differential traces.

• Differential trace lengths should be matched as close as possible to minimize phase imbalance and HD2

degradation.

2. Digital JESD204B output interface

• Traces should be routed using tightly coupled 100-Ω differential traces.

3. Power and ground connections

• Provide low resistance connection paths to all power and ground pins.

• Use power and ground planes instead of traces.

• Avoid narrow, isolated paths which increase the connection resistance.

• Use a signal/ground/power circuit board stackup to maximize coupling between the ground and power

plane.

8.5.2 Layout Example

The following screen shot shows the top layer of the ADC32RF5x EVM.

• The input signal traces are routed as differential signals on the top layer avoiding vias. Care is taken

to maintain symmetry between positive and negative input with matched trace length to minimize phase

imbalance.

Figure 8-7 shows the layout example for 1x and 2x averaging configuration

Figure 8-8 shows the layout example for 4x averaging configuration

• JESD204B output interface lanes are routed differential and length matched

• Bypass caps are close to the power pins on the top layer avoiding vias.

ADC32RF52

SBASAI6 – SEPTEMBER 2023

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ADC32RF52 Datasheet(PDF) 98 Page - Texas Instruments