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ADC32RF52 Datasheet(PDF) 73 Page - Texas Instruments

Part # ADC32RF52
Description  ADC32RF52 Dual Channel 14-bit 1.5-GSPS RF Sampling Data Converter
PDF  108 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADC32RF52 Datasheet(HTML) 73 Page - Texas Instruments

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Figure 7-68. Register 0x2D (JESD page)
7
6
5
4
3
2
1
0
0
0
0
0
0
JESD SEQ SEL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 7-75. Register 0x2D Field Descriptions
Bit
Field
Type
Reset
Description
7-3
0
R/W
0
Must write 0
2-0
JESD SEQ SEL
R/W
000
This register selects the JESD test pattern sequence
0: Test sequence disabled
1: Repeat D21.5 high frequency pattern for random jitter (RJ)
2: Repeat K28.5 mixed frequency pattern for deterministic jitter
(DJ)
3: Repeat initial lane alignment (ILA) sequence
4: Modified random pattern
5: Scrambled jitter pattern
6: Repeat K28.7 low frequency pattern
7: Short test pattern
Figure 7-69. Register 0x2E (JESD page)
7
6
5
4
3
2
1
0
RAMP INCR
0
RAMP EN
ALT PAT
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 7-76. Register 0x2E Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RAMP INCR
R/W
0000
This register value sets the increment step size for the ramp
pattern on 16-bit output. The step size is RAMP INCR plus 1.
3
0
R/W
0
Must write 0
2
RAMP EN
R/W
0
Enables RAMP output pattern in the TRANSPORT LAYER.
1
ALT PAT
R/W
0
Enables a toggle pattern switching between 0x0000 and 0xFFFF
in the TRANSPORT LAYER
0
0
R/W
0
Must write 0
Figure 7-70. Register 0x2F (JESD page)
7
6
5
4
3
2
1
0
0
SERDES PRBS
SERDES PRBS
EN
0
0
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 7-77. Register 0x2F Field Descriptions
Bit
Field
Type
Reset
Description
7
0
R/W
0
Must write 0
6-5
SERDES PRBS
R/W
0
This register selects the PRBS pattern in the LINK LAYER (no
8b/10b encoding). PRBS pattern must be enabled (D4).
0: PRBS 27-1
1: PRBS 215-1
2: PRBS 223-1
3: PRBS 231-1
4
SERDES PRBS EN
R/W
0
This register enables PRBS test pattern in the LINK LAYER
0: Test pattern mode disabled
1: PRBS test pattern mode enabled
3-0
0
R/W
0
Must write 0
www.ti.com
ADC32RF52
SBASAI6 – SEPTEMBER 2023
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: ADC32RF52



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