ADC32RF52 datasheet(13/108 Pages) TI

13 / 108 page

6.9 Timing Requirements (continued)

Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages.

Typical values are specified at TA = 25°C, ADC sampling rate = 1.5 GSPS, Bypass mode, 50% clock duty cycle, AVDD18 =

1.8V, AVDD12, AVDDCLK, DVDD = 1.2V and –1-dBFS differential input, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fCLK(SCLK) Serial clock frequency

MHz

tSU(SEN)

SEN to rising edge of SCLK

tH(SEN)

SEN from rising edge of SCLK

tSU(SDIO)

SDIO to rising edge of SCLK

tH(SDIO)

SDIO from rising edge of SCLK

SERIAL PROGRAMMING INTERFACE (SDIO) - Output

t(OZD)

SDIO tri-state to driven

t(ODZ)

SDIO data to tri-state

t(OD)

SDIO valid from falling edge of SCLK

TIMING: SYSREFP/M

ts(SYSREF)

Setup time, SYSREFP/M valid to rising edge

of CLKP/M

th(SYSREF)

Hold time, SYSREFP/M valid to rising edge

of CLKP/M

CML SERDES OUTPUTS: DA[0:3]P/M, DB[0:3]P/M

fSerdes

Serdes bit rate

0.5

12.8

13.0

Gbps

Random jitter, RMS

RPAT, 6.4 Gbps

0.7

RPAT, 12.8 Gbps

0.6

Deterministic jitter, peak to peak

RPAT, 6.4 Gbps

8.9

RPAT, 12.8 Gbps

14.7

Total jitter, peak to peak

RPAT, 6.4 Gbps

19.5

RPAT, 12.8 Gbps

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ADC32RF52

SBASAI6 – SEPTEMBER 2023

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