ATMEGA48 datasheet(131/374 Pages) ATMEL

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131

2545J–AVR–12/06

ATmega48/88/168

Note:

1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In

this case the compare match is ignored, but the set or clear is done at BOTTOM. See Section

“14.9.3” on page 121. for more details.

Table 14-3 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase

correct or the phase and frequency correct, PWM mode.

Note:

1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See

Section “14.9.4” on page 123. for more details.

• Bit 1:0 – WGM11:0: Waveform Generation Mode

Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting

sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-

form generation to be used, see Table 14-4. Modes of operation supported by the Timer/Counter

unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types

of Pulse Width Modulation (PWM) modes. (See Section “14.9” on page 120.).

Table 14-3.

Compare Output Mode, Phase Correct and Phase and Frequency Correct

PWM(1)

COM1A1/COM1B1

COM1A0/COM1B0

Description

Normal port operation, OC1A/OC1B disconnected.

WGM13:0 = 9 or 11: Toggle OC1A on Compare

Match, OC1B disconnected (normal port operation).

For all other WGM1 settings, normal port operation,

OC1A/OC1B disconnected.

Clear OC1A/OC1B on Compare Match when up-

counting. Set OC1A/OC1B on Compare Match when

downcounting.

Set OC1A/OC1B on Compare Match when up-

counting. Clear OC1A/OC1B on Compare Match

when downcounting.

ATMEGA48 Datasheet(PDF) 131 Page - ATMEL Corporation