ATMEGA48 datasheet(36/374 Pages) ATMEL

36 / 374 page

2545J–AVR–12/06

ATmega48/88/168

Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is

used, it is the divided system clock that is output.

7.10

Timer/Counter Oscillator

The device can operate its Timer/Counter2 from an external 32.768 kHz watch crystal or a exter-

nal clock source. The Timer/Counter Oscillator Pins (TOSC1 and TOSC2) are shared with

XTAL1 and XTAL2. This means that the Timer/Counter Oscillator can only be used when an

internal RC Oscillator is selected as system clock source. See Figure 7-2 on page 30 for crystal

connection.

Applying an external clock source to TOSC1 requires EXTCLK in the ASSR Register written to

logic one. See ”Asynchronous Operation of Timer/Counter2” on page 151 for further description

on selecting external clock as input instead of a 32 kHz crystal.

7.11

System Clock Prescaler

The ATmega48/88/168 has a system clock prescaler, and the system clock can be divided by

setting the ”CLKPR – Clock Prescale Register” on page 377. This feature can be used to

decrease the system clock frequency and the power consumption when the requirement for pro-

cessing power is low. This can be used with all clock source options, and it will affect the clock

frequency of the CPU and all synchronous peripherals. clk

I/O, clkADC, clkCPU, and clkFLASH are

divided by a factor as shown in Table 27-3 on page 307.

When switching between prescaler settings, the System Clock Prescaler ensures that no

glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than

neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-

sponding to the new setting. The ripple counter that implements the prescaler runs at the

frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it

is not possible to determine the state of the prescaler - even if it were readable, and the exact

time it takes to switch from one clock division to the other cannot be exactly predicted. From the

time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new

clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the pre-

vious clock period, and T2 is the period corresponding to the new prescaler setting.

To avoid unintentional changes of clock frequency, a special write procedure must befollowed to

change the CLKPS bits:

Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bitsin

CLKPR to zero.

Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure the write procedure is

not interrupted.

ATMEGA48 Datasheet(PDF) 36 Page - ATMEL Corporation