ATMEGA48 datasheet(41/374 Pages) ATMEL

41 / 374 page

2545J–AVR–12/06

ATmega48/88/168

If Timer/Counter2 is not running, Power-down mode is recommended instead of Power-save

mode.

The Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save

mode. If Timer/Counter2 is not using the asynchronous clock, the Timer/Counter Oscillator is

stopped during sleep. If Timer/Counter2 is not using the synchronous clock, the clock source is

stopped during sleep. Note that even if the synchronous clock is running in Power-save, this

clock is only available for Timer/Counter2.

8.6

Standby Mode

When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the

SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down

with the exception that the Oscillator is kept running. From Standby mode, the device wakes up

in six clock cycles.

8.7

Power Reduction Register

The Power Reduction Register (PRR), see ”PRR – Power Reduction Register” on page 44, pro-

vides a method to stop the clock to individual peripherals to reduce power consumption. The

current state of the peripheral is frozen and the I/O registers can not be read or written.

Resources used by the peripheral when stopping the clock will remain occupied, hence the

peripheral should in most cases be disabled before stopping the clock. Waking up a module,

which is done by clearing the bit in PRR, puts the module in the same state as before shutdown.

Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall

power consumption. See ”Power-Down Supply Current” on page 323 for examples. In all other

sleep modes, the clock is already stopped.

8.8

Minimizing Power Consumption

There are several possibilities to consider when trying to minimize the power consumption in an

AVR controlled system. In general, sleep modes should be used as much as possible, and the

sleep mode should be selected so that as few as possible of the device’s functions are operat-

ing. All functions not needed should be disabled. In particular, the following modules may need

special consideration when trying to achieve the lowest possible power consumption.

8.8.1

Analog to Digital Converter

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-

abled before entering any sleep mode. When the ADC is turned off and on again, the next

conversion will be an extended conversion. Refer to ”Analog-to-Digital Converter” on page 244

for details on ADC operation.

8.8.2

Analog Comparator

When entering Idle mode, the Analog Comparator should be disabled if not used. When entering

ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes,

the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up

to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all

sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep

mode. Refer to ”Analog Comparator” on page 241 for details on how to configure the Analog

Comparator.

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