Table 5-1. Pin Functions (continued)

PIN

NET LENGTH

(mils)

SIGNAL

TYPE(1)

DESCRIPTION

NAME

NO.

RESERVED_VB

E3, F3,

K3, L3

NC

Do not connect on the DLP system board.

RESERVED_VR

B2, B3,

P2, P3

NC

Do not connect on the DLP system board.

(1)

I = Input, O = Output, G = Ground, A = Analog, P = Power, NC = No Connect.

(2)

Power supply pins required for all DMD operating modes are VSS, VBIAS, VCC, VCCI, VOFFSET, and VRESET.

(3)

VSS must be connected for proper DMD operation.

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted).(1)

MIN

MAX

UNIT

SUPPLY VOLTAGES

VCC

Supply voltage for LVCMOS core logic(2)

–0.5

4

V

VCCI

Supply voltage for LVDS interface(2)

–0.5

4

V

VOFFSET

Micromirror electrode and HVCMOS voltage(2) (3)

–0.5

9

V

VMBRST

Input voltage for MBRST(15:0)(2)

–28

28

V

|VCCI – VCC|

Supply voltage delta (absolute value)(4)

0.3

V

INPUT VOLTAGES

Input voltage for all other input pins(2)

–0.5

VCC + 0.3

V

|VID|

Input differential voltage (absolute value)(5)

700

mV

CLOCKS

ƒCLOCK

Clock frequency for LVDS interface, DCLK_A

400

MHz

ƒCLOCK

Clock frequency for LVDS interface, DCLK_B

400

MHz

ENVIRONMENTAL

TARRAY

Temperature, operating(6)

0

90

°C

Temperature, non-operating(6)

–40

90

°C

TDP

Dew point temperature, operating and non-operating (noncondensing)

81

°C

(1)

Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and

this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2)

All voltages are referenced to common ground VSS. VBIAS, VCC, VCCI, VOFFSET, and VRESET power supplies are all required for all DMD

operating modes.

(3)

VOFFSET supply transients must fall within specified voltages.

(4)

Exceeding the recommended allowable voltage difference between VCC and VCCI may result in excessive current draw.

(5)

The maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.

(6)

The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1

(TP1), shown in the figure in Section 7.5 .

(7)

VOFFSET supply transients must fall within specified voltages.

(8)

Excludes micromirror bias reset inputs MBRST(15:0).

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DLP651LE

DLPS153 – OCTOBER 2023

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