6.2 Storage Conditions

Applicable for the DMD as a component or non-operating in a system.

MIN

MAX

UNIT

TDMD

DMD storage temperature

–40

80

°C

TDP-AVG

Average dew point temperature (non-condensing) (1)

28

°C

TDP-ELR

Elevated dew point temperature range (non-condensing) (2)

28

36

°C

CTELR

Cumulative time in elevated dew point temperature range

24

Months

(1)

The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.

(2)

Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total

cumulative time of CTELR.

6.3 ESD Ratings

SYMBOL

PARAMETER

DESCRIPTION

VALUE

UNIT

V(ESD)

Electrostatic

discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)

±1000

V

Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)

±500

V

V(ESD)

Electrostatic

discharge (MBRST

PINS)

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001

±150

V

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in

this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is

implied when operating the device above or below these limits.

MIN NOM

MAX

UNIT

VOLTAGE SUPPLY

VCC

Supply voltage for LVCMOS core logic(1)

3.0

3.3

3.6

V

VCCI

Supply voltage for LVDS Interface(1)

3.0

3.3

3.6

V

VOFFSET

Micromirror Electrode and HVCMOS voltage(1) (2)

8.25

8.5

8.75

V

VMBRST

Micromirror Bias / Reset Voltage(1)

–27

26.5

V

|VCC – VCCI|

Supply voltage delta (absolute value)(3)

0

0.3

V

LVCMOS INTERFACE

VIH

Input High Voltage

1.7

2.5

VCC + 0.3

V

VIL

Input Low Voltage

–0.3

0.7

V

IOH

High Level Output Current

–20

mA

IOL

Low Level Output Current

15

mA

tPWRDNZ

PWRDNZ pulse width(4)

10

ns

SCP INTERFACE

ƒSCPCLK

SCP clock frequency(5)

50

500

kHz

tSCP_PD

Propagation delay, clock to Q, from rising-edge of SCPCLK to valid

SCPDO(6)

0

900

ns

tSCP_DS

SCPDI clock setup time (before SCPCLK falling-edge)(6)

800

ns

tSCP_DH

SCPDI hold time (after SCPCLK falling-edge)(6)

900

ns

tSCP_NEG_ENZ

Time between falling-edge of SCPENZ and the rising-edge of

SCPCLK(5)

1

us

SCP_POS_ENZ

Time between falling-edge of SCPCLK and the rising-edge of

SCPENZ

1

us

tSCP_OUT_EN

Time required for SCP output buffer to recover after SCPENZ

(from tristate)

192/ƒDCLK

s

DLP651LE

DLPS153 – OCTOBER 2023

www.ti.com

8

Submit Document Feedback

Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: DLP651LE