CX20921 AudioSmart Data Sheet

List of Figures

Conexant Confidential

03/11/15

001DSR01

V

List of Figures

Figure 1: CX20921 Block Diagram ................................................................................................................................................... 5

Figure 2: CX20921 Pin Configuration ............................................................................................................................................... 6

Figure 3: DC-DC Converter—Internal 1V ....................................................................................................................................... 14

Figure 4: SPI Transmit Timing ........................................................................................................................................................ 15

Figure 5: SPI Transmit and Receive Timing ................................................................................................................................... 16

Figure 6: I2C Bus Transactions ...................................................................................................................................................... 18

Figure 7: I2C Data Transfer Format................................................................................................................................................ 18

Figure 8: Interface Timing Requirements for 400kHz Transfer....................................................................................................... 19

Figure 9: DMIC................................................................................................................................................................................ 20

Figure 10: DMIC Timing.................................................................................................................................................................. 21

Figure 11: I2S Timing Diagram....................................................................................................................................................... 23

Figure 12: I2S Timing Diagram—16 Bits per Channel I2S ............................................................................................................. 23

Figure 13: Left-Justified Timing Diagram........................................................................................................................................ 24

Figure 14: Right-Justified Timing Diagram...................................................................................................................................... 24

Figure 15: Package Dimensions: 60-Pin QFN................................................................................................................................ 26

Figure 16: CX20921 Device PCB Footprint .................................................................................................................................... 28