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CX20921 Datasheet(PDF) 9 Page - Synaptics Incorporated. |
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CX20921 Datasheet(HTML) 9 Page - Synaptics Incorporated. |
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9 / 35 page ![]() CX20921 AudioSmart Data Sheet Features Conexant Confidential 03/11/15 001DSR01 3 Interfaces • Universal Serial Bus (USB) 2.0 full-speed USB Audio Class (UAC): – Supports up to five endpoints – Fully configurable endpoints • Stereo digital microphone Pulse Density Modulated (PDM) interface (muxed pin): – Clock frequency = 1.536MHz and 3.072MHz – Supported sample rates = 8kHz to 96kHz – Available gain boost range from 0dB to 48dB in 12dB steps • I2S: – Output supports: ■ Four-channel I2S output available through pin muxing ■ Three-wire or six-wire digital audio interface ■ Master and slave configuration ■ 8kHz up to 192kHz sample rates ■ 8-bit, 16-bit, and 24-bit sample width ■ Left-justified and Right-justified mode (I2S only) – Input supports: ■ Six-channel I2S available through pin muxing ■ Four-wire or five-wire digital audio interface ■ Master and slave configuration ■ 8kHz up to 192kHz sample rates ■ 8-bit, 16-bit, and 24-bit sample width ■ Left-justified and Right-justified mode (I2S only) • SPI master: – Five-wire interface with two slave chip select outputs – Second slave chip select is optional through pin muxing – Maximum clock frequency up to 50MHz • I2C slave: – Maximum clock frequency of 1MHz – Control and boot • One Universal Asynchronous Receiver/Transmitter (UART) interface—Maximum baud rate up to 1.5625Mbps • Sony/Philips Digital Interface Format (S/PDIF) Receiver (RX) (muxed pin) that supports sample rates from 44.1kHz up to 192kHz • One dedicated General Purpose Input/Output (GPIO)—One multiplexed with I2S_TX_CLK_2 Clocks • 24MHz crystal clock • On-chip programmable Phase Locked Loops (PLLs)—Five internal PLLs for the audio processor |
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