ISP1581BD datasheet(18/73 Pages) PHILIPS

18 / 73 page

Philips Semiconductors

ISP1581

USB 2.0 HS interface device

Objective speciﬁcation

Rev. 02 — 23 October 2000

18 of 73

9397 750 07648

9.3 Data ﬂow registers

9.3.1

Endpoint Index register (address: 2CH)

The Endpoint Index register selects a target endpoint for register access by the

microcontroller. The register consists of 1 byte and the bit allocation is shown in

Table 14. The following registers are indexed:

• Endpoint MaxPacketsize

• Endpoint Type

• Buffer Length

• Data Port

• Short Packet

• Control Function.

For example, to access the OUT data buffer of endpoint 1 via the Data Port register,

the Endpoint Index register has to be written ﬁrst with 02H.

Table 14: Endpoint Index register: bit allocation

Bit

Symbol

reserved

EP0SETUP

ENDPIDX[3:0]

DIR

Reset

00H

Bus reset

00H

Access

R/W

Table 15: Endpoint Index register: bit description

Bit

Symbol

Description

7 to 6

reserved

EP0SETUP

Selects the SETUP buffer for Endpoint 0:

0 — EP0 data buffer

1 — SETUP buffer.

Must be logic 0 for access to other endpoints than Endpoint 0.

4 to 1

ENDPIDX[3:0] Endpoint Index: Selects the target endpoint for register access

of Buffer Length, Control Function, Data Port, Endpoint Type,

MaxPacketSize and Short Packet.

DIR

Direction bit: Sets the target endpoint as IN or OUT endpoint:

0 — target endpoint refers to OUT (RX) FIFO

1 — target endpoint refers to IN (TX) FIFO.

Table 16: Addressing of Endpoint 0 buffers

Buffer name

EP0SETUP

ENDPIDX

DIR

SETUP

00H

Data OUT

00H

Data IN

00H

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