ISP1581BD datasheet(21/73 Pages) PHILIPS

21 / 73 page

Philips Semiconductors

ISP1581

USB 2.0 HS interface device

Objective speciﬁcation

Rev. 02 — 23 October 2000

21 of 73

9397 750 07648

9.3.5

Endpoint MaxPacketSize register (address: 04H)

This register determines the maximum packet size for all endpoints except Control 0.

The register contains 2 bytes and the bit allocation is given in Table 22.

Each time the register is written, the Buffer Length registers of all endpoints are

re-initialized to the FFOSZ ﬁeld value. The NTRANS bits control the number of

transactions allowed in a single micro-frame (for high-speed operation only).

Table 21: Buffer Length register: bit allocation

Bit

Symbol

DATACOUNT[15:8]

Reset

00H

Bus reset

00H

Access

R/W

Bit

Symbol

DATACOUNT[7:0]

Reset

00H

Bus reset

00H

Access

R/W

Table 22: Endpoint MaxPacketSize register: bit allocation

Bit

Symbol

reserved

NTRANS[1:0]

FFOSZ[10:8]

Reset

00H

Bus reset

00H

Access

R/W

Bit

Symbol

FFOSZ[7:0]

Reset

00H

Bus reset

00H

Access

R/W

Table 23: Endpoint MaxPacketSize register: bit description

Bit

Symbol

Description

15 to 13

reserved

12 to 11

NTRANS[1:0]

Number of Transactions (HS mode only):

0 — 1 packet per microframe

1 — 2 packets per microframe

2 — 3 packets per microframe

3 — reserved.

10 to 0

FFOSZ[10:0]

FIFO Size: Sets the FIFO size in bytes for the indexed endpoint.

Applies to both HS and FS operation.

Remark: A FIFO size of zero will disable the endpoint.

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