ISP1581BD datasheet(3/73 Pages) PHILIPS

3 / 73 page

The direction of pins DREQ, DACK, DIOR and DIOW is determined by bit MASTER (DMA Hardware register) and bit ATA_MODE (DMA Conﬁguration register).

Fig 1.

Block diagram.

MGT234

1.5

Ω

12.2 k

Ω

(

±0.1%)

ISP1581

USB 2.0

TRANSCEIVER

3.3 V

RESET

RREF

3, 23

VOLTAGE

REGULATORS

POWER-ON

RESET

MEMORY

MANAGEMENT

UNIT

INTEGRATED

RAM

(8 KBYTE)

MICRO

CONTROLLER

INTERFACE

DMA

INTERFACE

MICRO-

CONTROLLER

HANDLER

DMA

HANDLER

DMA

REGISTERS

12 MHz

XTAL2

XTAL1

to/from USB

× PLL

OSCILLATOR

BIT CLOCK

RECOVERY

SYSTEM

CONTROLLER

PHILIPS

SIE

2, 37,

43, 64

SoftConnect

18, 17,

19, 20, 21

12, 13,

14, 15

40, 41,

44 to 57

READY

INT

internal

reset

analog

supply

3.3 V

DATA0 to DATA15

MODE0

*, MODE1

20, 9

BUS_CONF

38, 39, 30 to 35

25, 29, 26, 27

AD0 to AD7

DREQ, DACK,

DIOR, DIOW

CS0, CS1,

DA0

*, DA1*, DA2

VCC(5.0)

digital

supply

3.3 V

5 V

INTRQ

IORDY

*Denotes shared pin usage

RPU

−

Vreg(3.3)

24, 58

VCC(3.3)

SUSPEND

WAKEUP

AGND

1, 36, 42, 61

DGND

CS, ALE/A0, (R/W)/RD,

DS/WR

EOT

ISP1581BD Datasheet(PDF) 3 Page - NXP Semiconductors

ISP1581BD Datasheet(HTML) 3 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

Datasheet Download

Link URL