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ISP1581BD Datasheet(PDF) 39 Page - NXP Semiconductors |
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ISP1581BD Datasheet(HTML) 39 Page - NXP Semiconductors |
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39 / 73 page ![]() Philips Semiconductors ISP1581 USB 2.0 HS interface device Objective specification Rev. 02 — 23 October 2000 39 of 73 9397 750 07648 © Philips Electronics N.V. 2000. All rights reserved. 9.5.3 Frame Number register (address: 74H) This read-only register contains the frame number of the last successfully received Start Of Frame (SOF). The register contains 2 bytes and the bit allocation is given in Table 62. In case of 8-bit access the register content is returned lower byte first. Table 60: Chip ID register: bit allocation Bit 23 22 21 20 19 18 17 16 Symbol VERSION[7:0] Reset 01H Bus reset 01H Access R Bit 15 14 13 12 11 10 9 8 Symbol CHIPID[15:8] Reset 15H Bus reset 15H Access R Bit 7 6 5 4 3 2 1 0 Symbol CHIPID[7:0] Reset 81H Bus reset 81H Access R Table 61: Chip ID Register: bit description Bit Symbol Description 23 to 16 VERSION Version number (01H). The version number will be incremented in case of a silicon revision with improved performance and functionality. 15 to 8 CHIPID[15:8] Chip ID: upper byte (15H) 7 to 0 CHIPID[7:0] Chip ID: lower byte (81H) Table 62: Frame Number register: bit allocation Bit 15 14 13 12 11 10 9 8 Symbol reserved reserved MICROSOF[2:0] SOFR[10:8] Power Reset 0 0 00H 00H Bus Reset 0 0 00H 00H Access RR R R Bit 7 6 5 4 3 2 1 0 Symbol SOFR[7:0] Power Reset 00H Bus Reset 00H Access R |
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