AD9861 datasheet(24/52 Pages) AD

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AD9861

Rev. 0 | Page 24 of 52

degradation in SNR at a given full-scale input frequency (fINPUT),

due only to aperture jitter (tA), can be calculated with the

following equation:

SNR degradation

= 20 log [(½)πFINtA)]

In the equation, the rms aperture jitter, tA, represents the root-

sum-square of all jitter sources, which includes the clock input,

analog input signal, and ADC aperture jitter specification.

Undersampling applications are particularly sensitive to jitter.

The clock input is a digital signal that should be treated as an

analog signal with logic level threshold voltages, especially in

cases where aperture jitter may affect the dynamic range of the

AD9861. Power supplies for clock drivers should be separated

from the ADC output driver supplies to avoid modulating the

clock signal with digital noise. Low jitter crystal-controlled

oscillators make the best clock sources. If the clock is generated

from another type of source (by gating, dividing, or other meth-

ods), it should be retimed by the original clock at the last step.

Power Dissipation and Standby Mode

The power dissipation of the AD9861 Rx path is proportional to

its sampling rate. The Rx path portion of the digital (DRVDD)

power dissipation is determined primarily by the strength of the

digital drivers and the load on each output bit. The digital drive

current can be calculated by

IDRVDD

= VDRVDD × CLOAD × fCLOCK × N

where N is the number of bits changing and CLOAD is the average

load on the digital pins that changed.

The analog circuitry is optimally biased so that each speed

grade provides excellent performance while affording reduced

power consumption. Each speed grade dissipates a baseline

power at low sample rates, which increases with clock frequency.

The baseline power dissipation for either speed grade can be

reduced by asserting the ADC_LO_PWR pin, which reduces

internal ADC bias currents by half, in some case resulting in

degraded performance.

To further reduce power consumption of the ADC, the

ADC_LO_PWR pin can be combined with a serial programmable

ultralow power mode reduces the power consumption by a

fourth of the normal power consumption. The ultralow power

mode can be used at slower sampling frequencies or if reduced

performance is acceptable. To configure the ultralow power

mode, assert the ADC_LO_PWR pin and write the following

(MSB) ‘0000 1100’

(MSB) ‘0111 0000’

Either of the ADCs in the AD9861 Rx path can be placed in

standby mode independently by writing to the appropriate SPI

power is achieved when both channels are placed in full power-

down mode using the appropriate SPI register bits in Registers

3, 4, and 5. Under this condition, the internal references are

powered down. When either or both of the channel paths are

enabled after a power-down, the wake-up time is directly related

to the recharging of the REFT and REFB decoupling capacitors

and the duration of the power-down. Typically, it takes approxi-

mately 5 ms to restore full operation with fully discharged 0.1 µF

and 10 µF decoupling capacitors on REFT and REFB.

Tx PATH BLOCK

The AD9861 transmit (Tx) path includes dual interpolating

10-bit current output DACs that can be operated independently

or can be coupled to form a complex spectrum in an image

reject transmit architecture. Each channel includes two FIR

filters, making the AD9861 capable of 1×, 2×, or 4× interpola-

tion. High speed input and output data rates can be achieved

within the limitations of Table 9.

Table 9. AD9861 Tx Path Maximum Data Rate

Interpolation

Rate

20-Bit Interface

Mode

Input Data

Rate per

Channel

(MSPS)

DAC

Sampling

Rate

(MSPS)

FD, HD10, Clone

1×

HD20

160

FD, HD10, Clone

160

2×

HD20

160

FD, HD10, Clone

200

4×

HD20

200

By using the dual DAC outputs to form a complex signal, an

external analog quadrature modulator, such as the Analog

Devices AD8349, can enable an image rejection architecture.

(Note: the AD9861 evaluation board includes a quadrature

modulator in the Tx path that accommodates the AD8345,

AD8346 and the AD8345 footprints.) To optimize the image

rejection capability, as well as LO feedthrough suppression in

this architecture, the AD9861 offers programmable (via the SPI

port) fine (trim) gain and offset adjustment for each DAC.

Also included in the AD9861 are a phase-locked loop (PLL)

clock multiplier and a 1.2 V band gap voltage reference. With

the PLL enabled, a clock applied to the CLKIN input is multi-

plied internally and generates all necessary internal synchronization

clocks. Each 10-bit DAC provides two complementary current

outputs whose full-scale currents can be determined from a

single external resistor.

An external pin, TxPWRDWN, can be used to power down the

Tx path, when not used, to optimize system power consumption.

Using the TxPWRDWN pin disables clocks and some analog

circuitry, saving both digital and analog power. The power-down

mode leaves the biases enabled to facilitate a quick recovery

time, typically <10 µs. Additionally, a sleep mode is available,

which turns off the DAC output current, but leaves all other

circuits active, for a modest power savings. An SPI compliant

serial port is used to program the many features of the AD9861.

Note that in power-down mode, the SPI port is still active.

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