AD9861 datasheet(31/52 Pages) AD

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AD9861

Rev. 0 | Page 31 of 52

Table 12 describes AD9861 pin function (when mode pins are used) relative to I/O mode, and for half-duplex modes whether

transmitting or receiving.

Table 12. AD9861 Pin Function vs. Interface Mode (No SPI Cases)

Mode Name

U10

L10

IFACE1

IFACE2

IFACE3

Interleaved Tx Data

Interleaved Rx Data

TxSYNC

Buffered Rx Clock

Buffered Tx Clock

HD10

(Tx/Rx = High)

Interleaved Tx Data

MSB = TxSYNC

Others = Three-state

Tx/Rx = Tied High

10/20 Pin Control Tied High

Buffered Tx Clock

HD10

(Tx/Rx = Low)

MSB = RxSYNC

Others = Three-state

Interleaved Rx Data

Tx/Rx = Tied Low

10/20 Pin Control Tied High

Buffered Rx Clock

HD20

(Tx/Rx = High)

Tx_A Data

Tx_B Data

Tx/Rx = Tied High

10/20 Pin Control Tied Low

Buffered Tx Clock

HD20

(Tx/Rx = Low)

Rx_B Data

Rx_A Data

Tx/Rx = Tied Low

10/20 Pin Control Tied Low

Buffered Rx Clock

Clone Mode

(Tx/Rx = High)

Clone mode not available without SPI.

Clone Mode

(Tx/Rx = Low)

Clone mode not available without SPI.

Table 13 describes AD9861 pin function (when SPI programming is used) relative to flexible I/O mode, and for half-duplex modes

whether transmitting or receiving.

Table 13. AD9861 Pin Function vs. Interface Mode (Configured through the SPI Registers)

Mode Name

U10

L10

IFACE1

IFACE2

IFACE3

Interleaved Tx Data

Interleaved Rx Data

TxSYNC

Buffered System

Clock

Buffered Tx Clock

HD10, Tx Mode

(Tx/Rx = High)

Interleaved Tx Data

MSB = TxSYNC

Others = Three-state

Tx/Rx = Tied High

Optional Buffered

System Clock

Buffered Tx Clock

HD10, Rx Mode

(Tx/Rx = Low)

MSB = RxSYNC

Other = Three-state

Interleaved Tx Data

Tx/Rx = Tied Low

Optional Buffered

System Clock

Buffered Rx Clock

HD20, Tx Mode

(Tx/Rx = High)

Tx_A Data

Tx_B Data

Tx/Rx = Tied High

Optional Buffered

System Clock

Buffered Tx Clock

HD20, Rx Mode

(Tx/Rx = Low)

Rx_B Data

Rx_A Data

Tx/Rx = Tied Low

Optional Buffered

System Clock

Buffered Rx Clock

Clone Mode ,

Tx Mode

(Tx/Rx = High)

Interleaved Tx Data

MSB = TxSYNC

Others = Three-state

Tx/Rx = Tied High

Optional Buffered

System Clock

Buffered Tx Clock

Clone Mode ,

Rx Mode

(Tx/Rx = Low)

Rx_B Data

Rx_A Data

Tx/Rx = Tied Low

Optional Buffered

System Clock

Buffered Rx Clock

Summary of Flexible I/O Modes

FD Mode

The full-duplex (FD) mode can be configured by using mode

pins or with SPI programming. Using the SPI allows additional

configuration flexibility of the device.

FD mode is the only mode that supports full-duplex, receive,

and transmit concurrent operation. The upper 10-bit bus (U10)

is used to accept interleaved Tx data, and the lower 10-bit bus

(L10) is used to output interleaved Rx data. Either the Rx path

or the Tx path (or both) can be independently powered down

using either (or both) the RxPwrDwn and TxPwrDwn pins. FD

mode requires interpolation of 2× or 4×.

The following notes provide a general description of the FD

mode configuration. For more information, refer to Table 16.

Note the following about the Tx path in FD mode:

•

Interpolation rate of 2× or 4× can be programmed with

mode pins or SPI.

•

Max DAC update rate = 200 MSPS.

Max Tx input data rate = 80 MSPS/channel (160 MSPS

interleaved).

•

TxSYNC is used to direct Tx input data.

TxSYNC = high indicates channel Tx_A data.

TxSYNC = low indicates channel Tx_B data.

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