AD9861 datasheet(3/52 Pages) AD

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AD9861

Rev. 0 | Page 3 of 52

Tx PATH SPECIFICATIONS

Table 1. AD9861-50 and AD9861-80

FDAC = 200 MSPS; 4× interpolation; RSET = 4.02 kΩ; differential load resistance of 100 Ω1; TxPGA = 20 dB, AVDD = DVDD = 3.3 V,

unless otherwise noted

Parameter

Temp

Test Level

Min

Typ

Max

Unit

Tx PATH GENERAL

Resolution

Full

Bits

Maximum DAC Update Rate

Full

200

MHz

Maximum Full-Scale Output Current

Full

Full-Scale Error

Full

Gain Mismatch Error

25°C

–3.5

+3.5

% FS

Offset Mismatch Error

Full

–0.1

+0.1

% FS

Reference Voltage

Full

1.23

Output Capacitance

Full

Phase Noise (1 kHz Offset, 6 MHz Tone)

25°C

–115

dBc/Hz

Output Voltage Compliance Range

Full

–1.0

+1.0

TxPGA Gain Range

Full

TxPGA Step Size

Full

0.10

Tx PATH DYNAMIC PERFORMANCE

(IOUTFS = 20 mA; FOUT = 1 MHz)

SNR

Full

60.2

60.8

SINAD

Full

59.7

60.7

THD

Full

−77.5

−65.8

dBc

SFDR, Wideband (DC to Nyquist)

Full

64.6

76.0

dBc

SFDR, Narrowband (1 MHz Window)

Full

72.5

81.0

dBc

1 See Figure 2 for description of the TxDAC termination scheme.

03606-0-030

TxDAC

Ω

Figure 2. Diagram Showing Termination of 100 Ω Differential

Load for Some TxDAC Measurements

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