AD9861 datasheet(32/52 Pages) AD

32 / 52 page

AD9861

Rev. 0 | Page 32 of 52

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Buffered Tx clock output (from IFACE3 pin) equals 2× the

DAC update rate; one rising edge per interleaved Tx sample.

Note the following about the Rx path in FD mode:

•

ADC CLK Div register can be used to divide down the

clock driving the ADC, which accepts up to 50 MHz

(AD9861-50) or up to 80 MHz (AD9861-80).

•

Max ADC sampling rate = 50 MSPS (AD9861-50) or

80 MSPS (AD9861-80).

•

The Rx path output data rate is 2× the ADC sample rate

(interleaved).

•

Rx_A output when IFACE2 logic level = low.

Rx_B output when IFACE2 logic level = high.

HD10 Mode

The half-duplex, 10-bit interleaved outputs mode, HD10 can be

configured using mode pins or the SPI.

HD10 mode supports half-duplex only operations and can

interface to a single 10-bit data bus with independent Rx and Tx

synchronization pins (RxSYNC and TxSYNC). Both the U10

and L10 buses are used on the AD9861, but the logic level of the

Tx/Rx selector (controlled through IFACE1 pin) is used to

disable and three-state the unused bus, allowing U10 and L10 to

be tied together. The MSB of the unused bus acts as the RxSYNC

(during Rx operation) or TxSYNC (during Tx operation). A

single pin is used to output the clocks for Rx and Tx data

latching (from the IFACE3 pin) switching, depending on which

path is enabled. HD10 mode requires interpolation of 2× or 4×.

The following notes provide a general description of the HD10

mode configuration. For more information, refer to Table 16.

Note the following about the Tx path in HD10 mode:

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Interpolation rate of 2× or 4× can be programmed with

mode pins or SPI.

•

Interleaved Tx data accepted on U10 bus, L10 bus MSB acts

as TxSYNC.

•

Max DAC update rate = 200 MSPS.

Max Tx input data rate = 80 MSPS/channel (160 MSPS

interleaved).

•

TxSYNC is used to direct Tx input data.

TxSYNC = high indicates channel Tx_A data.

TxSYNC = low indicates channel Tx_B data.

Note the following about the Rx path in HD10 mode:

•

ADC CLK Div register can be used to divide down the

clock driving the ADC, which accepts up to 50 MHz

(AD9861-50) or up to 80 MHz (AD9861-80).

•

Max ADC sampling rate = 50 MSPS (AD9861-50) or

80 MSPS (AD9861-80).

•

Output data rate = 2× ADC sample rate.

•

Interleaved Rx data output from L10 bus.

•

Rx_A output when IFACE2 (or RxSYNC) logic level = low.

Rx_B output when IFACE2 (or RxSYNC) logic level = high.

HD20 Mode

The half-duplex 20-bit parallel output, HD20, can be configured

using mode pins or through SPI programming.

HD20 mode supports half-duplex only operations and can

interface to a single 20-bit data bus (two parallel 10-bit buses).

Both the U10 and L10 buses are used on the AD9861. The logic

level of the Tx/Rx selector (controlled through IFACE1 pin) is

used to configure the buses as Rx outputs (during Rx operation)

or as Tx inputs (during Tx operation). A single pin is used to

output the clocks for Rx and Tx data latching (from the IFACE3

pin) switching, depending on which path is enabled.

The following notes provide a general description of the HD20

mode configuration. For more information, refer to Table 16.

Note the following about the Tx Path in HD20 mode:

•

Interpolation rate of 1×, 2×, or 4× can be programmed with

mode pins or SPI.

•

Max DAC update rate = 200 MSPS.

Max Tx input data rate = 160 MSPS/channel with bypassed

interpolation filters, 100 MSPS for 2× interpolation or

50 MSPS for 4× interpolation.

•

Tx_A DAC data is accepted from the U10 bus; Tx_B DAC

data is accepted from the L10 bus.

Note the following about the Rx path in HD20 mode:

•

ADC CLK Div register can be used to divide down the

clock driving the ADC, which accepts up to 50 MHz

(AD9861-50) or up to 80 MHz (AD9861-80).

•

Max ADC sampling rate = 50 MSPS (AD9861-50) or

80 MSPS (AD9861-80).

•

The Rx_A output data is output on L10 bus; the Rx_B

output data is output on U10 bus.

Clone Mode

An interface mode provides a similar interface to the AD9860

when used in half-duplex mode. This mode is referred to as

clone mode and requires SPI to configure.

Clone mode provides a parallel Rx data output (20 bits) while in

Rx mode, and accepts interleaved Tx data (10-bit) while in Tx

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