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ADS5547 Datasheet(PDF) 23 Page - Texas Instruments

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Part # ADS5547
Description  12-BIT, 210 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
PDF  57 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADS5547 Datasheet(HTML) 23 Page - Texas Instruments

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ADS5527
SLWS196A – DECEMBER 2006 – REVISED MAY 2007
PIN CONFIGURATION (LVDS MODE) (continued)
PIN ASSIGNMENTS – LVDS Mode (continued)
PIN
PIN
NUMBER
PIN NAME
DESCRIPTION
TYPE
NUMBER
OF PINS
This pin functions as serial interface clock input when RESET is low.
It functions as LOW SPEED control pin when RESET is tied high. Tie SCLK to
SCLK
I
29
1
LOW for Fs > 50 MSPS and SCLK to HIGH for Fs
≤ 50 MSPS. See Table 3.
The pin has an internal 100-k
Ω pull-down resistor.
This pin functions as serial interface data input when RESET is low. It functions
as STANDBY control pin when RESET is tied high.
SDATA
I
28
1
See Table 4 for detailed information.
The pin has an internal 100 k
Ω pull-down resistor.
This pin functions as serial interface enable input when RESET is low. It functions
as CLKOUT edge programmability when RESET is tied high. See Table 5 for
SEN
I
27
1
detailed information.
The pin has an internal 100-k
Ω pull-up resistor to DRVDD.
Output buffer enable input, active high. The pin has an internal 100-k
Ω pull-up
OE
I
7
1
resistor to DRVDD.
Data Format Select input. This pin sets the DATA FORMAT (Twos complement or
DFS
Offset binary) and the LVDS/CMOS output mode type. See Table 6 for detailed
I
6
1
information.
Mode select input. This pin selects the Internal or External reference mode. See
MODE
I
23
1
Table 7 for detailed information.
CLKOUTP
Differential output clock, true
O
5
1
CLKOUTM
Differential output clock, complement
O
4
1
D0_D1_P
Differential output data D0 and D1 multiplexed, true
O
38
1
D0_D1_M
Differential output data D0 and D1 multiplexed, complement.
O
37
1
D2_D3_P
Differential output data D2 and D3 multiplexed, true
O
40
1
D2_D3_M
Differential output data D2 and D3 multiplexed, complement
O
39
1
D4_D5_P
Differential output data D4 and D5 multiplexed, true
O
42
1
D4_D5_M
Differential output data D4 and D5 multiplexed, complement
O
41
1
D6_D7_P
Differential output data D6 and D7 multiplexed, true
O
44
1
D6_D7_M
Differential output data D6 and D7 multiplexed, complement
O
43
1
D8_D9_P
Differential output data D8 and D9 multiplexed, true
O
46
1
D8_D9_M
Differential output data D8 and D9 multiplexed, complement
O
45
1
D10_D11_P
Differential output data D10 and D11 multiplexed, true
O
48
1
D10_D11_M
Differential output data D10 and D11 multiplexed, complement
O
47
1
OVR
Out-of-range indicator, CMOS level signal
O
3
1
DRVDD
Digital and output buffer supply
I
2, 35
2
DRGND
Digital and output buffer ground
I
1, 36
2
31, 32, 33,
NC
Do not connect
4
34
Connect the pad to the ground plane. See Board Design Considerations in
PAD
0
1
application information section.
23
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