ADS5547 datasheet(32/57 Pages) TI

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APPLICATION INFORMATION

THEORY OF OPERATION

ANALOG INPUT

Resr

200 W

Lpkg

6nH

10 W

Sampling

Capacitor

Csamp

2.4pF

INP

INM

Cbond

2pF

50 W

Cpar1

0.8pF

Cpar2

1pF

Ron

15 W

Ron

10 W

Ron

15 W

Cpar2

1pF

50 W

1.6pF

Lpkg

6nH

10 W

Cbond

2pF

Resr

200 W

Csamp

2.4pF

Sampling

Capacitor

Sampling

Switch

Sampling

Switch

R-C-RFilter

Drive Circuit Requirements

ADS5527

SLWS196A – DECEMBER 2006 – REVISED MAY 2007

ADS5527 is a low power 12-bit 210 MSPS pipeline ADC in a CMOS process. ADS5527 is based on switched

capacitor technology and runs off a single 3.3-V supply. The conversion process is initiated by a rising edge of

the external input clock. Once the signal is captured by the input sample and hold, the input sample is

sequentially converted by a series of lower resolution stages, with the outputs combined in a digital correction

logic block. At every clock edge, the sample propagates through the pipeline resulting in a data latency of 14

clock cycles. The output is available as 12-bit data, in DDR LVDS or CMOS and coded in either straight offset

binary or binary 2’s complement format.

The analog input consists of a switched-capacitor based differential sample and hold architecture, shown in

Figure 39.

This differential topology results in good ac-performance even for high input frequencies at high sampling rates.

The INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V available on VCM

pin 13. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM +

0.5 V and VCM – 0.5 V, resulting in a 2-VPP differential input swing. The maximum swing is determined by the

internal reference voltages REFP (2.5 V nominal) and REFM (0.5 V, nominal).

Figure 39. Input Stage

The input sampling circuit has a high 3-dB bandwidth that extends up to 800 MHz (measured from the input pins

to the voltage across the sampling capacitors)

The input sampling circuit of the ADS5527 has a high 3-dB analog bandwidth of 800 MHz making it possible to

sample input signals up to very high frequencies. To get best performance, it is recommended to have an

external R-C-R filter across the input pins (Figure 40). This helps to filter the glitches due to the switching of the

sampling capacitors. The R-C-R filter has to be designed to provide adequate filtering (for good performance)

and at the same time ensure sufficient bandwidth over the desired frequency range.

In addition, it is recommended to have a 15-

Ω series resistor on each input line to damp out ringing caused by

the package parasitic. At higher input frequencies (> 100 MHz), a lower series resistance around 5

Ω to 10 Ω

should be used. It is also necessary to present low impedance (< 50

Ω) for the common-mode switching

currents. For example, this could be achieved by using two resistors from each input terminated to the

common-mode voltage (Vcm).

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