CDC706PW datasheet(35/41 Pages) TI

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EVMBoardConfiguration:

• CLK_IN:Crystal27MHz

Measurement:

• StartCondition: ƒ(M =10,N=30)=81MHz

• Byte2write:N=30(81MHz) N=1

10(297MHz)

Result:

• 60 mstoPLL PullIn

• 90 mstoPLL PhaseLock

20 ms/div

297

t[ s]

StartCondition:

Acknowledgeof

N-DividerByte

Frequency

Response

Curveof Y0

VCO (MHz)

• Y0(PLL1), Y13state

• measuredChannel: Y0

Power Supply Sequencing

Device Behavior During Supply Voltage Drops

Typ3.3V

Typ2.1V

Typ1.7V

VCC

VPUC_ON

VPUC_OFF

GND

CDC706

SCAS829A – SEPTEMBER 2006 – REVISED MARCH 2007

Figure 33. Snapshot of the PLL Lock-Time

The CDC706 includes three power supply pins, VCC, VCCOUT1, and VCCOUT2. There are no power supply

sequencing requirements, as the three power nodes are separated from each other. So, power can be supplied

in any order to the three nodes.

Also, the part has a power-up circuitry which switches the device on if VCC exceeds 2.1 V (typical) and switches

the device off at VCC < 1.7 V (typical). In power-down mode, all outputs and clock inputs are switched off.

The CDC706 has a Power-Up-Circuit, which activates the device function at VPUC_ON (typical 2.1 V). At the same

time, the ROM information is loaded into the register. This mechanism ensures that there is a pre-defined default

after Power-Up and no need to reprogram the CDC706 in the application.

In the event of a supply-voltage-drop, the Power-Up-Circuit assures that there is always a defined setup within

the register. Figure 34 shows possible voltage drops with different amplitudes.

Figure 34. Different Voltage Drops on VCC During Operation

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