CDC706PW datasheet(6/41 Pages) TI

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DEVICE CHARACTERISTICS

CDC706

SCAS829A – SEPTEMBER 2006 – REVISED MARCH 2007

over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure 1

PARAMETER

TEST CONDITIONS

MIN TYP(1)

MAX

UNIT

OVERALL PARAMETER

All PLLs on, all outputs on,

ICC

Supply current (2)

fOUT = 80 MHz, fCLK_IN = 27 MHz,

115

f(VCO) = 160 MHz

Power down current. Every circuit

ICCPD

fIN = 0 MHz, VCC = 3.6 V

µA

powered down except SMBus

Supply voltage VCC threshold for

V(PUC)

2.1

power up control circuit

All PLLs

200

Normal speed-mode(3)

VCO frequency of internal PLL (any

f(VCO)

PLL2 with SSC

167

MHz

of three PLLs)

High-speed mode(3)

180

300

VCC = 2.5 V

250

LVCMOS output frequency range(4),

fOUT

MHz

See Figure 4

VCC = 3.3 V

300

LVCMOS PARAMETER

V(IK)

LVCMOS input voltage

VCC = 3 V, II = –18 mA

–1.2

LVCMOS input current (CLK_IN0 and

VI = 0 V or VCC, VCC = 3.6 V

±5

µA

CLK_IN1)

IIH

LVCMOS input current (S1/S0)

VI = VCC, VCC = 3.6 V

µA

IIL

LVCMOS input current (S1/S0)

VI = 0 V, VCC = 3.6 V

-35

-10

µA

Input capacitance at CLK_IN0 and

VI = 0 V or VCC

CLK_IN1

LVCMOS PARAMETER FOR VCCOUT = 3.3-V Mode

VCCOUT = 3 V, IOH = –0.1 mA

2.9

VOH

LVCMOS high-level output voltage

VCCOUT = 3 V, IOH = –4 mA

2.4

VCCOUT = 3 V, IOH = –6 mA

2.1

VCCOUT = 3 V, IOL = 0.1 mA

0.1

VOL

LVCMOS low-level output voltage

VCCOUT = 3 V, IOL = 4 mA

0.5

VCCOUT = 3 V, IOL = 6 mA

0.85

All PLL bypass

tPLH,

Propagation delay

tPHL

VCO bypass

Rise and fall time for output

tr0/tf0

VCCOUT = 3.3 V (20%–80%)

1.7

3.3

4.8

slew rate 0

Rise and fall time for output

tr1/tf1

VCCOUT = 3.3 V (20%–80%)

1.5

2.5

3.2

slew rate 1

Rise and fall time for output

tr2/tf2

VCCOUT = 3.3 V (20%–80%)

1.2

1.6

2.1

slew rate 2

Rise and fall time for output

tr3/tf3

VCCOUT = 3.3 V (20%–80%)

0.4

0.6

slew rate 3 (default configuration)

fOUT = 50 MHz

1 PLL, 1 Output

fOUT = 245.76 MHz

tjit(cc)

Cycle-to-cycle jitter (5)(6)

fOUT = 50 MHz

125

155

3 PLLs, 3 Outputs

fOUT = 245.76 MHz

(1)

All typical values are at respective nominal VCC.

(2)

For calculating total supply current, add the current from Figure 2, Figure 3, and Figure 4. Using high-speed mode of the VCO reduces

the current consumption. See Figure 3.

(3)

Normal-speed mode or high-speed mode must be selected by the VCO frequency selection bit in Byte 6, Bit [7:5]. The min f(VCO) can be

lower but impacts jitter-performance.

(4)

Do not exceed the maximum power dissipation of the 20-pin TSSOP package (600 mW at no air flow). See Figure 5

(5)

50000 cycles.

(6)

Jitter depends on configuration. Jitter data is normal tr/tf, input frequency = 3.84 MHz, f(VCO) = 245.76 MHz.

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