CDC706PW datasheet(23/41 Pages) TI

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2LVCMOS

Differential

input

CLK_IN0

CLK_IN1

Inputsourceselect

(fromSMBUS)

PLL Configuration and Setting

MUX

9−Bit Divider M

1 .. 511

PLLx

12−Bit Divider N

1 .. 4095

PFD

Filter

VCO

SSC

(PLL2 only)

Input Clock

Programming

PLL output

SSC output

(PLL2 Only)

VCO Bypass

CDC706

SCAS829A – SEPTEMBER 2006 – REVISED MARCH 2007

Differential Clock Inputs

The CDC706 supports differential signaling as well. In this mode, CLK_IN0 and CLK_IN1 pin serve as

differential signal inputs and can be driven up to 200 MHz.

The minimum magnitude of the differential input voltage is 100 mV over a differential common-mode input

voltage range of 200 mV to VCC– 0.6. If LVDS or LVPECL signal levels are applied, ac-coupling and a biasing

structure is recommended to adjust the different physical layers (see Figure 17). The capacitor removes the dc

component of the signal (common-mode voltage), while the ac component (voltage swing) is passed on. A

resistor pull-up and/or pull-down network represents the biasing structure used to set the common-mode voltage

on the receiver side of the ac-coupling capacitor. DC coupling is also possible.

Figure 17. Differential Clock Input Circuitry

The CDC706 includes three PLLs which are equal in function and performance. Except PLL2 which in addition

supports spread spectrum clocking (SSC) generation. Figure 18 shows the block diagram of the PLL.

Figure 18. PLL Architecture

All three PLLs are designed for easiest configuration. The user just has to define the input and output

frequencies or the divider (M, N, P) setting respectively. All other parameters, such as charge-pump current,

filter components, phase margin, or loop bandwidth are controlled and set by the device itself. This assures

optimized jitter attenuation and loop stability.

The PLL support normal-speed mode (80 MHz

≤ f

VCO ≤ 200 MHz) and high-speed mode (180 MHz ≤ fVCO ≤ 300

MHz) which can be selected by PLLxFVCO (Bit [7:5] of Byte 6). The respective speed option assures stable

operation and lowest jitter.

The divider M and divider N operates internally as fractional divider for fVCO up to 250 MHz. This allows fractional

divider ratio for zero ppm output clock error.

In case of fVCO > 250 MHz, it is recommended that integer factors of N/M are used only.

For optimized jitter performance, keep divider M as small as possible. Also, the fractional divider concept

requires a PLL divider configuration, M

≤ N (or N/M ≥ 1).

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