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V

CC

R

INT

TMDS

Receiver

w/EQ

TMDS

Driver

TX2

TX2

RX2

RX2

TMDS

Receiver

w/EQ

TMDS

Driver

TX1

TX1

RX1

RX1

TMDS

Receiver

w/EQ

TMDS

Driver

TX0

TX0

RX0

RX0

TMDS

Receiver

w/EQ

TMDS

Driver

TXC

TXC

RXC

RXC

R

INT

R

INT

R

INT

V

CC

V

CC

V

CC

VSADJ

PRE

RSCL

RSDA

TSCL

TSDA

I2CEN

OE

OVS

TMDS141

SLLS737B – JUNE 2006 – REVISED APRIL 2007

With standard TMDS terminations at the outputs, all TMDS outputs are forced high-impedance when OE is set

voltage is less than 1.5 V or I2CEN is low. The OVS pin, output voltage select, provides the flexibility of

adjusting the output voltage level of the TSCL and TSDA side to optimize noise margins while interfacing to

different HDMI receivers. The device is characterized for operation from 0

°C to 70°C.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

FUNCTIONAL BLOCK DIAGRAM

2

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