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PCA5007 Datasheet(PDF) 44 Page - NXP Semiconductors |
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PCA5007 Datasheet(HTML) 44 Page - NXP Semiconductors |
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44 / 112 page ![]() 1998 Oct 07 44 Philips Semiconductors Product specification Pager baseband controller PCA5007 Table 40 Baud rate for bits BD2, BD1 and BD0 6.17.3 DEMODULATOR AVERAGING REGISTER (DMD1) The demodulator averaging register DMD1 contains the control bit for enabling the averaging function, used for the offset compensation during demodulation and the coded average (offset) value. Table 41 Demodulator Averaging Register (DMD1, SFR address EDH) Table 42 Description of the DMD1 bits BITS BAUD RATE BD2 BD1 BD0 0 0 0 1200 symbols/s 0 0 1 2400 symbols/s 0 1 0 1600 symbols/s 0 1 1 3200 symbols/s 1 0 0 undefined 1 0 1 undefined 1 1 0 undefined 1 1 1 undefined 76543210 ENA AVG6 AVG5 AVG4 AVG3 AVG2 AVG1 AVG0 BIT SYMBOL FUNCTION DMD1.7 ENA enable averaging function/offset calculation DMD1.6 AVG6 7-bit value indicating the offset value of the demodulator. This is an indication of the LO offset frequency and will be used to determine the AFC output voltage. For coding see Table 37. DMD1.5 AVG5 DMD1.4 AVG4 DMD1.3 AVG3 DMD1.2 AVG2 DMD1.1 AVG1 DMD1.0 AVG0 |
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