PCA5007 datasheet(97/112 Pages) PHILIPS

97 / 112 page

1998 Oct 07

Philips Semiconductors

Product speciﬁcation

Pager baseband controller

PCA5007

15.2.1

SIGNALS FOR THE PARALLEL PROGRAMMING MODE

In this configuration, the following signals are necessary to program the OTP:

Table 63 Pins for programming mode

The control signals GBMbpB, PGM, LS1 and LS0 can be used to select the latches of the interface block and the internal

data latches of the OTP. Table 64 shows how the latches are selected.

RdStrb is used to open the selected latch. If PGM is not active the RdSTrb signal is used to start the OTP read cycle.

Table 64 Latch selection

OTP PIN

TYPE

EPROM

DESCRIPTION

COMMENTS

VPP

supply

VPP

programming voltage

special pin/logic signal not time critical

VDD

supply

VDD

positive supply

GND

supply

GND

negative supply

P0.7 to P0.0

I/O

A<14:0>

address

20 kbyte addresses available

Q<7:0>

data output

I<7:0>

data input

PS<2:0>

security bits input

connected to P0.2 to P0.0 pins

QS<2:0>

security bits output

P2.0/LS0

input

−

latch select 0

latch select signals, see Table 64

P2.1/LS1

input

−

latch select 1

P2.2/PGM

input

−

programming mode

P2.3/RdStrb

input

CEP/MBPC read/strobe

read enable Clock (CEP) when PGM = 0;

strobe for the latches when PGM = 1

P2.4/GBMbpB

input

output enable not/

Mult.BProg Not

read EPROM and set P0 as output; multiple byte

programming when PGM = 1

P2.5/WEB

input

WEB

Write Enable not

programs data if VPP is present

P2.6/SEC

input

SEC

select security bits

see Section 15.10

P2.7/SIG

input

SIG

read signature bytes

see Section 15.9

P2.4/GBMbpB

P2.2/PGM

P2.1/LS1

P2.1/LS0

DESCRIPTION

no latches selected

select test control latch

select lower address latch

select upper address latch

select internal data latch in multi byte programming

mode

PCA5007 Datasheet(PDF) 97 Page - NXP Semiconductors

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