ATA6621 datasheet(14/27 Pages) ATMEL

14 / 27 page

4887D–AUTO–12/06

ATA6621

After ramping up the battery voltage V

S or wake up from Sleep Mode, the 5V regulator is

switched on. The reset output NRES stays low for the time t

reset (typically 10 ms), then it

switches to high and the watchdog waits for the watchdog sequence from the microcontroller.

This lead time t

d follows after the reset and is td = 49 ms. After wake up from Silent Mode the

RXD switches to low. The lead time t

d follows the negative edge of this RXD signal. In this time,

the first watchdog pulse from the microcontroller is required. If the trigger pulse NTRIG (or

PTRIG, as the case may be) occurs during this time, the time t

1 starts immediately. If no trigger

signal occurs during the time t

d, a watchdog reset with tNRES = 1.96 ms will reset the microcon-

troller after t

d = 49 ms. The times t1 and t2 have a fixed relationship with each other. A triggering

signal from the microcontroller is anticipated within the time frame of t

2 = 10.5 ms. To avoid false

triggering from glitches, the trigger pulse must be longer than t

trigg > 3 µs. This slope serves to

restart the watchdog sequence. Should the triggering signal fail in this open window t

2, the

NRES output will be drawn to ground after t

2. A triggering signal during the closed window t1

causes NRES to immediately switch low.

Figure 3-8.

Timing Sequence with R

WD_OSC = 51 kΩ

3.17.2

Worst Case Calculation with R

WO_OSC = 51 kΩ

The internal oscillator has a tolerance of ±20%. This means that t

1 and t2 can also vary by ±20%.

The worst case calculation for the watchdog period T

wd the microcontroller has to provide is cal-

culated as follows.

The ideal watchdog time T

wd is between (t1maximum) and (t1 minimum plus t2 minimum).

1,min =0.8 × t1 =8ms, t1,max =1.2 × t1 =12ms

2,min = 0.8 × t2 = 8.4 ms, t2,max = 1.2 × t2 = 12.6 ms

wdmax =t1min + t2min = 8 ms + 8.4 ms = 16.4 ms

wdmin =t1max = 12 ms

wd = 14.2 ms ±2.2 ms (±15%)

tnres = 1.9 ms

Undervoltage Reset

Watchdog Reset

treset = 10 ms

t1 = 10 ms

ttrigg > 3 µs

t2 = 10.5 ms

twd

td = 49 ms

VCC = 5V

PTRIG

NTRIG

NRES

ATA6621 Datasheet(PDF) 14 Page - ATMEL Corporation

ATA6621 Datasheet(HTML) 14 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

Datasheet Download

Link URL